On Fri, Oct 26, 2018 at 08:13:19PM +0530, Jagan Teki wrote:
> This series fixed the issues related to work DSI on 2-lane panel
> which is reported on previous version[1].
> 
> Few comments from previous version still in discussion, but I just
> send this version just to group all working changes together.
> anyway I will fix in this in next version if any.
> 
> PLL_MIPI min rate is still weird, I tried many possible dclock rate
> from panel driver to satisfy manual suggested min rate 500MHz but
> none working so eventually moved 300MHz. any inputs on this area
> are welcome.
> 
> All these changes are tested in 2-lane, 4-lane MIPI-DSI panels.
> 
> If anyone wants to test, use this repo [2] with WIP-A64-DSI branch.

A changelog would be nice here, and usually you shouldn't send a new
version while there is ongoing discussion on the previous version.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com