[PATCH 0/4] pinctrl: meson: fix pull bits

[PATCH 0/4] pinctrl: meson: fix pull bits

[Jerome Brunet]

This patchset fixes the inversion between pull (up/down) and pull enable
bits on the GPIO AO bank of all amlogic when have, except the axg family.

The problem has been found while testing bias setting on the libretech
aml-s905x-cc on GPIO_AO 5. Unfortunately the bias register of this bank is
not described in the public datasheet of the s905x, but it is in the
one of the A113D, which gave a clue.

This was tested on gxl libretech aml-s905x-cc. Since all Amlogic we have
got so far derive from each other, there is no reason for things to be
any different on the meson8(b).

I would have preferred to make a single patch to fix this but the commit
introducing the mistake the is different for each SoC, so a single patch
could be more difficult/annoying to backport.

Jerome Brunet (4):
  pinctrl: meson: fix gxbb ao pull register bits
  pinctrl: meson: fix gxl ao pull register bits
  pinctrl: meson: fix meson8 ao pull register bits
  pinctrl: meson: fix meson8b ao pull register bits

 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 2 +-
 drivers/pinctrl/meson/pinctrl-meson-gxl.c  | 2 +-
 drivers/pinctrl/meson/pinctrl-meson8.c     | 2 +-
 drivers/pinctrl/meson/pinctrl-meson8b.c    | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

-- 
2.17.2

[PATCH 1/4] pinctrl: meson: fix gxbb ao pull register bits

[Jerome Brunet]

AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf

Fixes: 468c234f9ed7 ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index 4ceb06f8a33c..4edeb4cae72a 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -830,7 +830,7 @@ static struct meson_bank meson_gxbb_periphs_banks[] = {
 
 static struct meson_bank meson_gxbb_aobus_banks[] = {
 	/*   name    first      last       irq    pullen  pull    dir     out     in  */
-	BANK("AO",   GPIOAO_0,  GPIOAO_13, 0, 13, 0,  0,  0, 16,  0,  0,  0, 16,  1,  0),
+	BANK("AO",   GPIOAO_0,  GPIOAO_13, 0, 13, 0,  16, 0, 0,   0,  0,  0, 16,  1,  0),
 };
 
 static struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
-- 
2.17.2

[PATCH 2/4] pinctrl: meson: fix gxl ao pull register bits

[Jerome Brunet]

AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf

Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
index 7dae1d7bf6b0..158f618f1695 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
@@ -807,7 +807,7 @@ static struct meson_bank meson_gxl_periphs_banks[] = {
 
 static struct meson_bank meson_gxl_aobus_banks[] = {
 	/*   name    first      last      irq	pullen  pull    dir     out     in  */
-	BANK("AO",   GPIOAO_0,  GPIOAO_9, 0, 9, 0,  0,  0, 16,  0,  0,  0, 16,  1,  0),
+	BANK("AO",   GPIOAO_0,  GPIOAO_9, 0, 9, 0,  16, 0, 0,   0,  0,  0, 16,  1,  0),
 };
 
 static struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
-- 
2.17.2

[PATCH 3/4] pinctrl: meson: fix meson8 ao pull register bits

[Jerome Brunet]

AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf

Fixes: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson8.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c
index c6d79315218f..86466173114d 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8.c
@@ -1053,7 +1053,7 @@ static struct meson_bank meson8_cbus_banks[] = {
 
 static struct meson_bank meson8_aobus_banks[] = {
 	/*   name    first     last         irq    pullen  pull    dir     out     in  */
-	BANK("AO",   GPIOAO_0, GPIO_TEST_N, 0, 13, 0,  0,  0, 16,  0,  0,  0, 16,  1,  0),
+	BANK("AO",   GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 16,  0,  0,  0,  0,  0, 16,  1,  0),
 };
 
 static struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
-- 
2.17.2

[PATCH 4/4] pinctrl: meson: fix meson8b ao pull register bits

[Jerome Brunet]

AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf

Fixes: 0fefcb6876d0 ("pinctrl: Add support for Meson8b")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson8b.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c
index bb2a30964fc6..647ad15d5c3c 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8b.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8b.c
@@ -906,7 +906,7 @@ static struct meson_bank meson8b_cbus_banks[] = {
 
 static struct meson_bank meson8b_aobus_banks[] = {
 	/*   name    first     lastc        irq    pullen  pull    dir     out     in  */
-	BANK("AO",   GPIOAO_0, GPIO_TEST_N, 0, 13, 0,  0,  0, 16,  0,  0,  0, 16,  1,  0),
+	BANK("AO",   GPIOAO_0, GPIO_TEST_N, 0, 13, 0,  16, 0, 0,  0,  0,  0, 16,  1,  0),
 };
 
 static struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
-- 
2.17.2

Re: [PATCH 0/4] pinctrl: meson: fix pull bits

[Linus Walleij]

On Mon, Oct 29, 2018 at 4:13 PM Jerome Brunet <jbrunet@baylibre.com> wrote:

> This patchset fixes the inversion between pull (up/down) and pull enable
> bits on the GPIO AO bank of all amlogic when have, except the axg family.
>
> The problem has been found while testing bias setting on the libretech
> aml-s905x-cc on GPIO_AO 5. Unfortunately the bias register of this bank is
> not described in the public datasheet of the s905x, but it is in the
> one of the A113D, which gave a clue.
>
> This was tested on gxl libretech aml-s905x-cc. Since all Amlogic we have
> got so far derive from each other, there is no reason for things to be
> any different on the meson8(b).
>
> I would have preferred to make a single patch to fix this but the commit
> introducing the mistake the is different for each SoC, so a single patch
> could be more difficult/annoying to backport.

All patches applied for fixes.
Thanks for drilling into this!

Yours,
Linus Walleij