From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53AFDC6786F for ; Thu, 1 Nov 2018 20:02:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1EFB720657 for ; Thu, 1 Nov 2018 20:02:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1EFB720657 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=paulk.fr Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727965AbeKBFG7 (ORCPT ); Fri, 2 Nov 2018 01:06:59 -0400 Received: from leonov.paulk.fr ([185.233.101.22]:46026 "EHLO leonov.paulk.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726717AbeKBFG6 (ORCPT ); Fri, 2 Nov 2018 01:06:58 -0400 Received: from gagarine.paulk.fr (gagarine [192.168.1.127]) by leonov.paulk.fr (Postfix) with ESMTPS id C271BBFC95; Thu, 1 Nov 2018 21:02:30 +0100 (CET) Received: by gagarine.paulk.fr (Postfix, from userid 114) id 5E1B0C1081; Thu, 1 Nov 2018 21:02:30 +0100 (CET) Received: from localhost.localdomain (collins [192.168.1.129]) by gagarine.paulk.fr (Postfix) with ESMTP id 30E31C105A; Thu, 1 Nov 2018 21:00:35 +0100 (CET) From: Paul Kocialkowski To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Thierry Reding , David Airlie , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , linux-sunxi@googlegroups.com, Paul Kocialkowski Subject: [PATCH NOT FOR MERGE v2 6/7] ARM: dts: sun7i: Add pinmux configuration for LCD0 RGB888 pins Date: Thu, 1 Nov 2018 21:00:44 +0100 Message-Id: <20181101200045.6078-7-contact@paulk.fr> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181101200045.6078-1-contact@paulk.fr> References: <20181101200045.6078-1-contact@paulk.fr> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds the pin muxing definition for configuring the PD pins in LCD0 mode for a RGB888 format to the sun7i device-tree. Signed-off-by: Paul Kocialkowski --- arch/arm/boot/dts/sun7i-a20.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 9c52712af241..26f3714eaad0 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -811,6 +811,17 @@ function = "ir1"; }; + lcd0_rgb888_pins: lcd0-rgb888 { + pins = "PD0", "PD1", "PD2", "PD3", + "PD4", "PD5", "PD6", "PD7", + "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD14", "PD15", + "PD16", "PD17", "PD18", "PD19", + "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + function = "lcd0"; + }; + mmc0_pins_a: mmc0@0 { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; -- 2.19.1