linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
To: x86@kernel.org, platform-driver-x86@vger.kernel.org,
	linux-sgx@vger.kernel.org
Cc: dave.hansen@intel.com, sean.j.christopherson@intel.com,
	nhorman@redhat.com, npmccallum@redhat.com, serge.ayoun@intel.com,
	shay.katz-zamir@intel.com, haitao.huang@intel.com,
	mark.shanahan@intel.com, andriy.shevchenko@linux.intel.com,
	Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	"H. Peter Anvin" <hpa@zytor.com>,
	linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT
	AND 64-BIT))
Subject: [PATCH v15 08/23] x86/sgx: Define SGX1 and SGX2 ENCLS leafs
Date: Sat,  3 Nov 2018 01:11:07 +0200	[thread overview]
Message-ID: <20181102231320.29164-9-jarkko.sakkinen@linux.intel.com> (raw)
In-Reply-To: <20181102231320.29164-1-jarkko.sakkinen@linux.intel.com>

ENCLS, a.k.a. Enclave System instruction, is an umbrella instruction
for a variety of privileged SGX functions.  The ENCLS function to be
executed is specified in EAX, a la GETSEC of SMX/TXT fame.  Leafs may
use additional registers for function-specific operands.  ENCLS also
introduces its own set of error codes that (some) leafs use to return
pass/fail information to software.  Leafs that return an error code
also modify RFLAGS.  And finally, ENCLS generates ENCLS-specific #GPs
and #PFs.

ENCLS leafs functions are organized under SGX sub-features, e.g. SGX1
defines the base ENCLS function set and SGX2 adds ENCLS functions to
enable dynamic EPC management.  At this time, only the SGX1 and SGX2
function sets are supported by Linux; the other published sets relate
to VMM EPC oversubscription, which is far out on the horizon.

Define the ENCLS leafs in a dedicated file as more architecturally
defined SGX constants and data structures will be introduced in short
order.

Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
---
 arch/x86/include/asm/sgx_arch.h | 54 +++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 arch/x86/include/asm/sgx_arch.h

diff --git a/arch/x86/include/asm/sgx_arch.h b/arch/x86/include/asm/sgx_arch.h
new file mode 100644
index 000000000000..e068db46835e
--- /dev/null
+++ b/arch/x86/include/asm/sgx_arch.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
+/**
+ * Copyright(c) 2016-18 Intel Corporation.
+ *
+ * Contains data structures defined by the SGX architecture.  Data structures
+ * defined by the Linux software stack should not be placed here.
+ */
+#ifndef _ASM_X86_SGX_ARCH_H
+#define _ASM_X86_SGX_ARCH_H
+
+/**
+ * enum sgx_encls_leaves - ENCLS leaf functions
+ * %SGX_ECREATE:	Create an enclave.
+ * %SGX_EADD:		Add a page to an uninitialized enclave.
+ * %SGX_EINIT:		Initialize an enclave, i.e. launch an enclave.
+ * %SGX_EREMOVE:	Remove a page from an enclave.
+ * %SGX_EDBGRD:		Read a word from an enclve (peek).
+ * %SGX_EDBGWR:		Write a word to an enclave (poke).
+ * %SGX_EEXTEND:	Measure 256 bytes of an added enclave page.
+ * %SGX_ELDB:		Load a swapped page in blocked state.
+ * %SGX_ELDU:		Load a swapped page in unblocked state.
+ * %SGX_EBLOCK:		Change page state to blocked i.e. entering hardware
+ *			threads cannot access it and create new TLB entries.
+ * %SGX_EPA:		Create a Version Array (VA) page used to store isvsvn
+ *			number for a swapped EPC page.
+ * %SGX_EWB:		Swap an enclave page to the regular memory. Checks that
+ *			all threads have exited that were in the previous
+ *			shoot-down sequence.
+ * %SGX_ETRACK:		Start a new shoot down sequence. Used to together with
+ *			EBLOCK to make sure that a page is safe to swap.
+ * %SGX_EAUG:		Add a page to an initialized enclave.
+ * %SGX_EMODPR:		Restrict an EPC page's permissions.
+ * %SGX_EMODT:		Modify the page type of an EPC page.
+ */
+enum sgx_encls_leaves {
+	SGX_ECREATE	= 0x00,
+	SGX_EADD	= 0x01,
+	SGX_EINIT	= 0x02,
+	SGX_EREMOVE	= 0x03,
+	SGX_EDGBRD	= 0x04,
+	SGX_EDGBWR	= 0x05,
+	SGX_EEXTEND	= 0x06,
+	SGX_ELDB	= 0x07,
+	SGX_ELDU	= 0x08,
+	SGX_EBLOCK	= 0x09,
+	SGX_EPA		= 0x0A,
+	SGX_EWB		= 0x0B,
+	SGX_ETRACK	= 0x0C,
+	SGX_EAUG	= 0x0D,
+	SGX_EMODPR	= 0x0E,
+	SGX_EMODT	= 0x0F,
+};
+
+#endif /* _ASM_X86_SGX_ARCH_H */
-- 
2.19.1


  parent reply	other threads:[~2018-11-02 23:15 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-02 23:10 [PATCH v15 00/23] Intel SGX1 Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 01/23] x86/sgx: Update MAINTAINERS Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 02/23] x86/cpufeatures: Add Intel-defined SGX feature bit Jarkko Sakkinen
2018-11-02 23:33   ` Borislav Petkov
2018-11-02 23:55     ` Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 03/23] x86/cpufeatures: Add SGX sub-features (as Linux-defined bits) Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 04/23] x86/msr: Add IA32_FEATURE_CONTROL.SGX_ENABLE definition Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 05/23] x86/cpu/intel: Detect SGX support and update caps appropriately Jarkko Sakkinen
2018-11-03 13:05   ` Andy Shevchenko
2018-11-05 14:09     ` Jarkko Sakkinen
2018-11-05 14:11       ` Jarkko Sakkinen
2018-11-05 14:31       ` Andy Shevchenko
2018-11-02 23:11 ` [PATCH v15 06/23] x86/mm: x86/sgx: Add new 'PF_SGX' page fault error code bit Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 07/23] x86/mm: x86/sgx: Signal SIGSEGV for userspace #PFs w/ PF_SGX Jarkko Sakkinen
2018-11-02 23:11 ` Jarkko Sakkinen [this message]
2018-11-02 23:11 ` [PATCH v15 09/23] x86/sgx: Add ENCLS architectural error codes Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 10/23] x86/sgx: Add SGX1 and SGX2 architectural data structures Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 11/23] x86/sgx: Add definitions for SGX's CPUID leaf and variable sub-leafs Jarkko Sakkinen
2018-11-03 13:11   ` Andy Shevchenko
2018-11-05 14:35     ` Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 12/23] x86/cpufeatures: Add Intel-defined SGX_LC feature bit Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 13/23] x86/msr: Add SGX Launch Control MSR definitions Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 14/23] x86/cpu/intel: Clear SGX_LC capability if not enabled in FEATURE_CONTROL Jarkko Sakkinen
2018-11-03 13:15   ` Andy Shevchenko
2018-11-05 14:37     ` Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 15/23] x86/sgx: Add wrappers for ENCLS leaf functions Jarkko Sakkinen
2018-11-03 13:17   ` Andy Shevchenko
2018-11-05 17:30     ` Jarkko Sakkinen
2018-11-05 20:39       ` Andy Shevchenko
2018-11-06 12:03         ` Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 16/23] x86/sgx: Enumerate and track EPC sections Jarkko Sakkinen
2018-11-03  1:07   ` Jethro Beekman
2018-11-05 17:31     ` Jarkko Sakkinen
2018-11-03 13:22   ` Andy Shevchenko
2018-11-05 17:35     ` Jarkko Sakkinen
2018-11-06 12:10     ` Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 17/23] x86/sgx: Add functions to allocate and free EPC pages Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 18/23] x86/sgx: Add sgx_einit() for initializing enclaves Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 19/23] platform/x86: Intel SGX driver Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 20/23] platform/x86: sgx: Add swapping functionality to the " Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 21/23] x86/sgx: Add a simple swapper for the EPC memory manager Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 22/23] platform/x86: ptrace() support for the SGX driver Jarkko Sakkinen
2018-11-02 23:11 ` [PATCH v15 23/23] x86/sgx: Driver documentation Jarkko Sakkinen
2018-11-04  8:15   ` Mike Rapoport
2018-11-05 17:39     ` Jarkko Sakkinen
2018-11-05 20:27   ` Dave Hansen
2018-11-06  5:49     ` Jarkko Sakkinen
2018-11-06  6:20       ` Jarkko Sakkinen
2018-11-06 16:45       ` Dave Hansen
2018-11-07 16:30         ` Jarkko Sakkinen
2018-11-07 17:09           ` Dave Hansen
2018-11-08 14:39             ` Jarkko Sakkinen
2018-11-08 19:20               ` Jarkko Sakkinen
2018-11-13 15:13                 ` Jarkko Sakkinen
2018-11-06  6:26     ` Jarkko Sakkinen

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181102231320.29164-9-jarkko.sakkinen@linux.intel.com \
    --to=jarkko.sakkinen@linux.intel.com \
    --cc=andriy.shevchenko@linux.intel.com \
    --cc=bp@alien8.de \
    --cc=dave.hansen@intel.com \
    --cc=haitao.huang@intel.com \
    --cc=hpa@zytor.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-sgx@vger.kernel.org \
    --cc=mark.shanahan@intel.com \
    --cc=mingo@redhat.com \
    --cc=nhorman@redhat.com \
    --cc=npmccallum@redhat.com \
    --cc=platform-driver-x86@vger.kernel.org \
    --cc=sean.j.christopherson@intel.com \
    --cc=serge.ayoun@intel.com \
    --cc=shay.katz-zamir@intel.com \
    --cc=tglx@linutronix.de \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).