From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA7FBC0044C for ; Mon, 5 Nov 2018 10:38:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9D80C20881 for ; Mon, 5 Nov 2018 10:38:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9D80C20881 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729401AbeKET5U (ORCPT ); Mon, 5 Nov 2018 14:57:20 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40352 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729349AbeKET5U (ORCPT ); Mon, 5 Nov 2018 14:57:20 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 484EBEBD; Mon, 5 Nov 2018 02:38:17 -0800 (PST) Received: from e107155-lin (e107155-lin.cambridge.arm.com [10.1.196.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E3D7C3F5BD; Mon, 5 Nov 2018 02:38:14 -0800 (PST) Date: Mon, 5 Nov 2018 10:38:07 +0000 From: Sudeep Holla To: Taniya Das Cc: Stephen Boyd , "Rafael J. Wysocki" , Viresh Kumar , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Rajendra Nayak , devicetree@vger.kernel.org, robh@kernel.org, skannan@codeaurora.org, linux-arm-msm@vger.kernel.org, amit.kucheria@linaro.org, evgreen@google.com, Sudeep Holla Subject: Re: [PATCH 2/2] cpufreq: qcom-hw: Add support for QCOM cpufreq HW driver Message-ID: <20181105103807.GA12647@e107155-lin> References: <1539257761-23023-1-git-send-email-tdas@codeaurora.org> <1539257761-23023-3-git-send-email-tdas@codeaurora.org> <153981915373.5275.15971019914218464179@swboyd.mtv.corp.google.com> <0c51a12e-38d3-2df5-4f5f-6a687727e9bf@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0c51a12e-38d3-2df5-4f5f-6a687727e9bf@codeaurora.org> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Nov 03, 2018 at 08:36:00AM +0530, Taniya Das wrote: > Hello Stephen, > > On 10/18/2018 5:02 AM, Stephen Boyd wrote: > > Quoting Taniya Das (2018-10-11 04:36:01) > > > --- a/drivers/cpufreq/Kconfig.arm > > > +++ b/drivers/cpufreq/Kconfig.arm [...] > > > +static const u16 cpufreq_qcom_std_offsets[REG_ARRAY_SIZE] = { > > > > Is this going to change in the future? > > > > Yes, they could change and that was the reason to introduce the offsets. > This was discussed earlier too with Sudeep and was to add them. Sorry, I didn't like these registers to be coming from DT and I had the same question: will this keep changing ? And IIRC, the answer was yes. But I agree with Stephen, if and when we see the change, you can introduce the array and keep it simple until then. -- Regards, Sudeep