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From: Chris Packham <chris.packham@alliedtelesis.co.nz>
To: linux@armlinux.org.uk, bp@alien8.de, arnd@arndb.de,
	jlu@pengutronix.de, gregory.clement@bootlin.com
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
	Chris Packham <chris.packham@alliedtelesis.co.nz>
Subject: [PATCH v6 2/9] ARM: aurora-l2: add prefix to MAX_RANGE_SIZE
Date: Fri,  9 Nov 2018 20:03:42 +1300	[thread overview]
Message-ID: <20181109070349.20464-3-chris.packham@alliedtelesis.co.nz> (raw)
In-Reply-To: <20181109070349.20464-1-chris.packham@alliedtelesis.co.nz>

From: Jan Luebbe <jlu@pengutronix.de>

The macro name is too generic, so add a AURORA_ prefix.

Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
 arch/arm/include/asm/hardware/cache-aurora-l2.h | 2 +-
 arch/arm/mm/cache-l2x0.c                        | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/hardware/cache-aurora-l2.h b/arch/arm/include/asm/hardware/cache-aurora-l2.h
index c86124769831..dc5c479ec4c3 100644
--- a/arch/arm/include/asm/hardware/cache-aurora-l2.h
+++ b/arch/arm/include/asm/hardware/cache-aurora-l2.h
@@ -41,7 +41,7 @@
 #define AURORA_ACR_FORCE_WRITE_THRO_POLICY	\
 	(2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
 
-#define MAX_RANGE_SIZE		1024
+#define AURORA_MAX_RANGE_SIZE	1024
 
 #define AURORA_WAY_SIZE_SHIFT	2
 
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index a00d6f7fd34c..7d2d2a3c67d0 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1364,8 +1364,8 @@ static unsigned long aurora_range_end(unsigned long start, unsigned long end)
 	 * since cache range operations stall the CPU pipeline
 	 * until completion.
 	 */
-	if (end > start + MAX_RANGE_SIZE)
-		end = start + MAX_RANGE_SIZE;
+	if (end > start + AURORA_MAX_RANGE_SIZE)
+		end = start + AURORA_MAX_RANGE_SIZE;
 
 	/*
 	 * Cache range operations can't straddle a page boundary.
-- 
2.19.1

  parent reply	other threads:[~2018-11-09  7:04 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-09  7:03 [PATCH v6 0/9] EDAC drivers for Armada XP L2 and DDR Chris Packham
2018-11-09  7:03 ` [PATCH v6 1/9] ARM: l2c: move cache-aurora-l2.h to asm/hardware Chris Packham
2018-11-09  7:03 ` Chris Packham [this message]
2018-11-09  7:03 ` [PATCH v6 3/9] ARM: aurora-l2: add defines for parity and ECC registers Chris Packham
2018-11-09  7:03 ` [PATCH v6 4/9] ARM: l2x0: support parity-enable/disable on aurora Chris Packham
2018-11-09  7:03 ` [PATCH v6 5/9] dt-bindings: ARM: document marvell,ecc-enable binding Chris Packham
2018-11-09 11:40   ` Arnd Bergmann
2018-11-09 11:48     ` Russell King - ARM Linux
2018-11-09 15:58       ` Arnd Bergmann
2018-11-11 19:57         ` Chris Packham
2018-11-11 22:35   ` Rob Herring
2018-11-09  7:03 ` [PATCH v6 6/9] ARM: l2x0: add marvell,ecc-enable property for aurora Chris Packham
2018-11-09  7:03 ` [PATCH v6 7/9] EDAC: Add missing debugfs_create_x32 wrapper Chris Packham
2018-11-09  7:03 ` [PATCH v6 8/9] EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC Chris Packham
2018-11-11 19:40   ` Borislav Petkov
2018-11-09  7:03 ` [PATCH v6 9/9] EDAC: armada_xp: Add support for more SoCs Chris Packham

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