From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7182C43441 for ; Fri, 9 Nov 2018 07:04:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9ECEF20883 for ; Fri, 9 Nov 2018 07:04:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="1jTz1c5T" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9ECEF20883 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=alliedtelesis.co.nz Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728126AbeKIQna (ORCPT ); Fri, 9 Nov 2018 11:43:30 -0500 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:45790 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728072AbeKIQna (ORCPT ); Fri, 9 Nov 2018 11:43:30 -0500 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 8969680237; Fri, 9 Nov 2018 20:04:15 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1541747055; bh=mTaA5V5SDbaoUTifccvwBOpV2UZw2RIkrTYYv2E8CzU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=1jTz1c5TLPep9gKDlRLjaR04Vu8HtoTwSKh5ihxAIa34IDInniZL2ITRWj+39hdYG dgkyVfrHOZ87H894jYZ90ErKELwMynXgzmJjD6XCvs/KdMirdWOHD2c0LDHVDoQ8dQ UV1Pc4mt66sI4V0hQ5siGoVvfGNn7CSe6WnRIx355C93c3f6kEgWquc6ChLCtj8Cra xsNuAvS9EsyndmnAdiobYaQ4JKZeekiW4TxboVnx6k/muSgHQIb17PN+Yd4nre2o7c q57Qif57JudVmlinTtxnSPX/Ikrw6L8SHtJUYMUrMOETW9kYlqY7xSPRDHwDRor3IE snU3OIEb0N+yQ== Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7,5,8,10121) id ; Fri, 09 Nov 2018 20:03:59 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id 5C86C13EEA1; Fri, 9 Nov 2018 20:04:04 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 398591E0BC9; Fri, 9 Nov 2018 20:03:59 +1300 (NZDT) From: Chris Packham To: linux@armlinux.org.uk, bp@alien8.de, arnd@arndb.de, jlu@pengutronix.de, gregory.clement@bootlin.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v6 2/9] ARM: aurora-l2: add prefix to MAX_RANGE_SIZE Date: Fri, 9 Nov 2018 20:03:42 +1300 Message-Id: <20181109070349.20464-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181109070349.20464-1-chris.packham@alliedtelesis.co.nz> References: <20181109070349.20464-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable x-atlnz-ls: pat Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jan Luebbe The macro name is too generic, so add a AURORA_ prefix. Signed-off-by: Jan Luebbe Reviewed-by: Gregory CLEMENT Signed-off-by: Chris Packham --- =20arch/arm/include/asm/hardware/cache-aurora-l2.h | 2 +- =20arch/arm/mm/cache-l2x0.c | 4 ++-- =202 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/hardware/cache-aurora-l2.h b/arch/arm/i= nclude/asm/hardware/cache-aurora-l2.h index c86124769831..dc5c479ec4c3 100644 --- a/arch/arm/include/asm/hardware/cache-aurora-l2.h +++ b/arch/arm/include/asm/hardware/cache-aurora-l2.h @@ -41,7 +41,7 @@ =20#define AURORA_ACR_FORCE_WRITE_THRO_POLICY \ =20 (2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) =20 -#define MAX_RANGE_SIZE 1024 +#define AURORA_MAX_RANGE_SIZE 1024 =20 =20#define AURORA_WAY_SIZE_SHIFT 2 =20 diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index a00d6f7fd34c..7d2d2a3c67d0 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1364,8 +1364,8 @@ static unsigned long aurora_range_end(unsigned long= =20start, unsigned long end) =20 * since cache range operations stall the CPU pipeline =20 * until completion. =20 */ - if (end > start + MAX_RANGE_SIZE) - end =3D start + MAX_RANGE_SIZE; + if (end > start + AURORA_MAX_RANGE_SIZE) + end =3D start + AURORA_MAX_RANGE_SIZE; =20 =20 /* =20 * Cache range operations can't straddle a page boundary. --=20 2.19.1