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From: Jagan Teki <jagan@amarulasolutions.com>
To: Maxime Ripard <maxime.ripard@bootlin.com>,
	Chen-Yu Tsai <wens@csie.org>, Icenowy Zheng <icenowy@aosc.io>,
	Jernej Skrabec <jernej.skrabec@siol.net>,
	Vasily Khoruzhick <anarsoul@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>,
	David Airlie <airlied@linux.ie>,
	dri-devel@lists.freedesktop.org,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	linux-clk@vger.kernel.org,
	Michael Trimarchi <michael@amarulasolutions.com>,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,
	linux-amarula@amarulasolutions.com
Cc: Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH v4 15/26] drm/sun4i: sun6i_mipi_dsi: Set proper vblk timing calculation
Date: Tue, 13 Nov 2018 16:46:22 +0530	[thread overview]
Message-ID: <20181113111633.20189-16-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20181113111633.20189-1-jagan@amarulasolutions.com>

Unlike hblk, the vblk timings should follow an equation to compute
the desired value for lane 4 devices and rest of devices it would be 0.

BSP code from BPI-M64-bsp is computing vblk as for 4-lane devices
(from linux-sunxi
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)

tmp = (ht*dsi_pixel_bits[format]/8)*vt-(4+dsi_hblk+2);
dsi_vblk = (lane-tmp%lane);

So, update the vblk timing calculation accordingly.

Tested on 2-lane, 4-lane MIPI-DSI LCD panels.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 32 ++++++++++++++++++++------
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 63b924b89bd7..703722f7c81b 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -355,6 +355,30 @@ static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
 		     SUN6I_DSI_INST_JUMP_CFG_NUM(1));
 };
 
+static u16 sun6i_dsi_get_timings_vblk(struct sun6i_dsi *dsi,
+				      struct drm_display_mode *mode, u16 hblk)
+{
+	struct mipi_dsi_device *device = dsi->device;
+	u16 vblk = 0;
+
+	/*
+	 * The vertical blank is set using a blanking packet (4 bytes +
+	 * payload + 2 bytes). Its minimal size is therefore 6 bytes
+	 */
+#define VBLK_PACKET_OVERHEAD	6
+	if (device->lanes == 4) {
+		unsigned int Bpp;
+		int tmp;
+
+		Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
+		tmp = (mode->htotal * Bpp) * mode->vtotal -
+		      (hblk + VBLK_PACKET_OVERHEAD);
+		vblk = (device->lanes - tmp % device->lanes);
+	}
+
+	return vblk;
+}
+
 static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
 					   struct drm_display_mode *mode)
 {
@@ -503,13 +527,7 @@ static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi,
 		   (mode->htotal - (mode->hsync_end - mode->hsync_start)) *
 		   Bpp - HBLK_PACKET_OVERHEAD);
 
-	/*
-	 * And I'm not entirely sure what vblk is about. The driver in
-	 * Allwinner BSP is using a rather convoluted calculation
-	 * there only for 4 lanes. However, using 0 (the !4 lanes
-	 * case) even with a 4 lanes screen seems to work...
-	 */
-	vblk = 0;
+	vblk = sun6i_dsi_get_timings_vblk(dsi, mode, hblk);
 
 	/* How many bytes do we need to send all payloads? */
 	bytes = max_t(size_t, max(max(hfp, hblk), max(hsa, hbp)), vblk);
-- 
2.18.0.321.gffc6fa0e3


  parent reply	other threads:[~2018-11-13 11:18 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-13 11:16 [PATCH v4 00/26] drm/sun4i: Allwinner A64 MIPI-DSI support Jagan Teki
2018-11-13 11:16 ` [PATCH v4 01/26] clk: sunxi-ng: a64: Fix gate bit of DSI DPHY Jagan Teki
2018-11-13 13:08   ` Maxime Ripard
2018-11-13 11:16 ` [PATCH v4 02/26] clk: sunxi-ng: Add check for minimal rate to NKM PLLs Jagan Teki
2018-11-13 11:16 ` [PATCH v4 03/26] clk: sunxi-ng: Add check for maximum " Jagan Teki
2018-11-13 13:26   ` Maxime Ripard
2018-11-15 15:21     ` Jagan Teki
2018-11-20 10:55       ` Maxime Ripard
2018-11-20 12:07         ` Jagan Teki
2018-11-13 11:16 ` [PATCH v4 04/26] drm/sun4i: sun6i_mipi_dsi: Add has_mod_clk quirk Jagan Teki
2018-11-13 11:16 ` [PATCH v4 05/26] drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support Jagan Teki
2018-11-13 11:16 ` [PATCH v4 06/26] dt-bindings: sun6i-dsi: Add compatible for A64 MIPI DSI Jagan Teki
2018-11-13 11:16 ` [PATCH v4 07/26] drm/sun4i: sun6i_mipi_dsi: Add DSI Generic short write 2 param transfer Jagan Teki
2018-11-13 11:16 ` [PATCH v4 08/26] drm/sun4i: sun6i_mipi_dsi: Fix VBP size calculation Jagan Teki
2018-11-15  9:55   ` Maxime Ripard
2018-11-15 17:49     ` Jagan Teki
2018-11-20 15:57       ` Maxime Ripard
2018-11-20 16:25         ` Jagan Teki
2018-11-26 12:07           ` [linux-sunxi] " Jagan Teki
2018-11-27 10:25             ` Maxime Ripard
2018-11-27 10:24           ` Maxime Ripard
2018-11-27 11:04             ` [linux-sunxi] " Jagan Teki
2018-12-07 13:21               ` Maxime Ripard
2018-12-10 16:07                 ` Jagan Teki
2018-11-13 11:16 ` [PATCH v4 09/26] drm/sun4i: sun6i_mipi_dsi: Fix TCON DRQ set bits Jagan Teki
2018-11-13 11:16 ` [PATCH v4 10/26] drm/sun4i: sun6i_mipi_dsi: Refactor vertical video start delay Jagan Teki
2018-11-13 11:16 ` [PATCH v4 11/26] drm/sun4i: sun6i_mipi_dsi: Fix DSI hbp timing value Jagan Teki
2018-11-13 11:16 ` [PATCH v4 12/26] drm/sun4i: sun6i_mipi_dsi: Fix DSI hblk timing calculation Jagan Teki
2018-11-13 11:16 ` [PATCH v4 13/26] drm/sun4i: sun6i_mipi_dsi: Add DSI hblk packet overhead Jagan Teki
2018-11-13 11:16 ` [PATCH v4 14/26] drm/sun4i: sun6i_mipi_dsi: Fix DSI hfp timing value Jagan Teki
2018-11-13 11:16 ` Jagan Teki [this message]
2018-11-13 11:16 ` [PATCH v4 16/26] drm/sun4i: sun6i_mipi_dsi: Add support for VCC-DSI voltage regulator Jagan Teki
2018-11-13 11:16 ` [PATCH v4 17/26] dt-bindings: sun6i-dsi: Add VCC-DSI supply property Jagan Teki
2018-11-16 23:19   ` Rob Herring
2018-11-13 11:16 ` [PATCH v4 18/26] dt-bindings: panel: Add Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB bridge Jagan Teki
2018-11-13 11:16 ` [PATCH v4 19/26] drm/panel: " Jagan Teki
2018-11-13 11:16 ` [PATCH v4 20/26] dt-bindings: panel: Add Techstar TS8550B MIPI-DSI panel Jagan Teki
2018-11-13 11:16 ` [PATCH v4 21/26] drm/panel: Add Techstar TS8550B MIPI-DSI LCD panel Jagan Teki
2018-11-13 11:16 ` [PATCH v4 22/26] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI Jagan Teki
2018-11-13 11:16 ` [PATCH v4 23/26] dt-bindings: sun6i-dsi: Add compatible for A64 DPHY Jagan Teki
2018-11-13 11:16 ` [PATCH v4 24/26] arm64: dts: allwinner: a64: Add DSI pipeline Jagan Teki
2018-11-13 11:16 ` [PATCH v4 25/26] [DO NOT MERGE] arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel Jagan Teki
2018-11-13 12:22   ` Andre Przywara
2018-11-14  6:31     ` Jagan Teki
2018-11-14  6:58       ` Chen-Yu Tsai
2018-11-14  9:22         ` Chen-Yu Tsai
2018-11-14 11:18           ` Jagan Teki
2018-11-13 11:16 ` [PATCH v4 26/26] arm64: dts: allwinner: a64-amarula-relic: Enable Techstar TS8550B MIPI-DSI panel Jagan Teki
2018-11-13 12:32   ` Andre Przywara

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