From: Jagan Teki <jagan@amarulasolutions.com>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <maxime.ripard@bootlin.com>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>,
Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Icenowy Zheng <icenowy@aosc.io>,
Jernej Skrabec <jernej.skrabec@siol.net>,
Vasily Khoruzhick <anarsoul@gmail.com>,
Thierry Reding <thierry.reding@gmail.com>,
Mark Rutland <mark.rutland@arm.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Michael Trimarchi <michael@amarulasolutions.com>,
TL Lim <tllim@pine64.org>,
linux-sunxi@googlegroups.com, linux-amarula@amarulasolutions.com
Cc: Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH v2 07/12] drm/sun4i: sun6i_mipi_dsi: Setup burst mode
Date: Fri, 16 Nov 2018 22:09:11 +0530 [thread overview]
Message-ID: <20181116163916.29621-8-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20181116163916.29621-1-jagan@amarulasolutions.com>
Setting up burst mode display would require to compute
- Horizontal timing edge values to fill burst drq register
- Line, sync values to fill burst line register
Since there is no direct documentation for these computations
the edge and line formulas are taken from BSP code (from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
line_num = panel->lcd_ht*dsi_pixel_bits[panel->lcd_dsi_format]/
(8*panel->lcd_dsi_lane);
edge1 = sync_point+(panel->lcd_x+panel->lcd_hbp+20)*
dsi_pixel_bits[panel->lcd_dsi_format] /(8*panel->lcd_dsi_lane);
edge1 = (edge1>line_num)?line_num:edge1;
edge0 = edge1+(panel->lcd_x+40)*tcon_div/8;
edge0 = (edge0>line_num)?(edge0-line_num):1;
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 72 ++++++++++++++++++++++++--
1 file changed, 68 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 66a01061e51d..0182408f8932 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -364,6 +364,41 @@ static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
SUN6I_DSI_INST_JUMP_CFG_NUM(1));
};
+static u32 sun6i_dsi_get_edge1(struct sun6i_dsi *dsi,
+ struct drm_display_mode *mode, u32 sync_point)
+{
+ struct mipi_dsi_device *device = dsi->device;
+ unsigned int bpp = mipi_dsi_pixel_format_to_bpp(device->format);
+ u32 hact_sync_bp;
+
+ /* Horizontal timings duration excluding front porch */
+ hact_sync_bp = (mode->hdisplay + mode->htotal - mode->hsync_start);
+
+ return (sync_point + ((hact_sync_bp + 20) * bpp / (8 * device->lanes)));
+}
+
+static u32 sun6i_dsi_get_edge0(struct sun6i_dsi *dsi,
+ struct drm_display_mode *mode, u32 edge1)
+{
+ struct sun4i_tcon *tcon = dsi->tcon;
+ unsigned long dclk_rate, dclk_parent_rate, tcon0_div;
+
+ dclk_rate = clk_get_rate(tcon->dclk);
+ dclk_parent_rate = clk_get_rate(clk_get_parent(tcon->dclk));
+ tcon0_div = dclk_parent_rate / dclk_rate;
+
+ return (edge1 + (mode->hdisplay + 40) * tcon0_div / 8);
+}
+
+static u32 sun6i_dsi_get_line_num(struct sun6i_dsi *dsi,
+ struct drm_display_mode *mode)
+{
+ struct mipi_dsi_device *device = dsi->device;
+ unsigned int bpp = mipi_dsi_pixel_format_to_bpp(device->format);
+
+ return (mode->htotal * bpp / (8 * device->lanes));
+}
+
static int sun6i_dsi_get_drq(struct sun6i_dsi *dsi,
struct drm_display_mode *mode)
{
@@ -499,9 +534,32 @@ static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi,
struct drm_display_mode *mode)
{
- regmap_write(dsi->regs, SUN6I_DSI_TCON_DRQ_REG,
- SUN6I_DSI_TCON_DRQ_ENABLE_MODE |
- SUN6I_DSI_TCON_DRQ_SET(sun6i_dsi_get_drq(dsi, mode)));
+ struct mipi_dsi_device *device = dsi->device;
+ u32 sync_point = 40;
+ u32 line_num = sun6i_dsi_get_line_num(dsi, mode);
+ u32 edge1 = sun6i_dsi_get_edge1(dsi, mode, sync_point);
+ u32 edge0 = sun6i_dsi_get_edge0(dsi, mode, edge1);
+ u32 val;
+
+ if (edge1 > line_num)
+ edge1 = line_num;
+
+ if (edge0 > line_num)
+ edge0 -= line_num;
+ else
+ edge0 = 1;
+
+ regmap_write(dsi->regs, SUN6I_DSI_BURST_DRQ_REG,
+ SUN6I_DSI_BURST_DRQ_EDGE1(edge1) |
+ SUN6I_DSI_BURST_DRQ_EDGE0(edge0));
+ regmap_write(dsi->regs, SUN6I_DSI_BURST_LINE_REG,
+ SUN6I_DSI_BURST_LINE_NUM(line_num) |
+ SUN6I_DSI_BURST_LINE_SYNC_POINT(sync_point));
+
+ /* enable burst mode */
+ regmap_read(dsi->regs, SUN6I_DSI_BASIC_CTL_REG, &val);
+ val |= SUN6I_DSI_BASIC_CTL_VIDEO_BURST;
+ regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL_REG, val);
}
static void sun6i_dsi_setup_inst_loop(struct sun6i_dsi *dsi,
@@ -726,7 +784,13 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION |
SUN6I_DSI_BASIC_CTL1_VIDEO_MODE);
- sun6i_dsi_setup_burst(dsi, mode);
+ regmap_write(dsi->regs, SUN6I_DSI_TCON_DRQ_REG,
+ SUN6I_DSI_TCON_DRQ_ENABLE_MODE |
+ SUN6I_DSI_TCON_DRQ_SET(sun6i_dsi_get_drq(dsi, mode)));
+
+ if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
+ sun6i_dsi_setup_burst(dsi, mode);
+
sun6i_dsi_setup_inst_loop(dsi, mode);
sun6i_dsi_setup_format(dsi, mode);
sun6i_dsi_setup_timings(dsi, mode);
--
2.18.0.321.gffc6fa0e3
next prev parent reply other threads:[~2018-11-16 16:40 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-16 16:39 [PATCH v2 00/12] drm/sun4i: Allwinner MIPI-DSI Burst mode support Jagan Teki
2018-11-16 16:39 ` [PATCH v2 01/12] drm/sun4i: sun6i_mipi_dsi: Compute burst mode loop N1 instruction delay Jagan Teki
2018-11-19 8:27 ` Maxime Ripard
2018-11-19 10:58 ` Jagan Teki
2018-11-20 13:23 ` Maxime Ripard
2018-11-20 13:36 ` Jagan Teki
2018-11-20 15:58 ` Maxime Ripard
2018-11-20 16:01 ` Vasily Khoruzhick
2018-11-20 16:19 ` Jagan Teki
2018-11-16 16:39 ` [PATCH v2 02/12] drm/sun4i: sun6i_mipi_dsi: Support instruction loop selection Jagan Teki
2018-11-16 16:39 ` [PATCH v2 03/12] drm/sun4i: sun6i_mipi_dsi: Setup burst mode timings Jagan Teki
2018-11-19 8:30 ` Maxime Ripard
2018-11-19 11:00 ` Jagan Teki
2018-11-20 15:45 ` Maxime Ripard
2018-11-20 16:22 ` Jagan Teki
2018-11-27 10:07 ` Maxime Ripard
2018-11-16 16:39 ` [PATCH v2 04/12] drm/sun4i: sun6i_mipi_dsi: Simplify drq set to support all modes Jagan Teki
2018-11-19 8:32 ` Maxime Ripard
2018-11-19 11:22 ` Jagan Teki
2018-11-20 14:32 ` Maxime Ripard
2018-11-20 14:48 ` Jagan Teki
2018-11-16 16:39 ` [PATCH v2 05/12] drm/sun4i: tcon: Export get tcon0 routine Jagan Teki
2018-11-19 8:34 ` Maxime Ripard
2018-11-16 16:39 ` [PATCH v2 06/12] drm/sun4i: sun6i_mipi_dsi: Probe tcon0 during dsi_bind Jagan Teki
2018-11-19 8:38 ` Maxime Ripard
2018-11-19 11:36 ` Jagan Teki
2018-11-20 15:44 ` Maxime Ripard
2018-11-16 16:39 ` Jagan Teki [this message]
2018-11-16 16:39 ` [PATCH v2 08/12] drm/sun4i: sun6i_mipi_dsi: Enable 2byte trail for 4-lane burst mode Jagan Teki
2018-11-16 16:39 ` [PATCH v2 09/12] drm/sun4i: sun6i_mipi_dsi: Enable burst mode HBP, HSA_HSE Jagan Teki
2018-11-16 16:39 ` [PATCH v2 10/12] dt-bindings: panel: Add Feiyang FY07024DI26A30-D MIPI-DSI LCD panel Jagan Teki
2018-11-16 16:39 ` [PATCH v2 11/12] drm/panel: " Jagan Teki
2018-12-10 16:12 ` Jagan Teki
2018-12-13 15:07 ` Sean Paul
2018-12-13 19:26 ` Jagan Teki
2018-12-13 19:55 ` Sean Paul
2018-12-14 11:05 ` Jagan Teki
2018-12-14 14:15 ` Sean Paul
2018-11-16 16:39 ` [PATCH v2 12/12][DO NOT MERGE] arm64: allwinner: a64: pine64-lts: Enable Feiyang FY07024DI26A30-D DSI panel Jagan Teki
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