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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id t2sm13868196pfm.32.2018.11.17.10.12.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 17 Nov 2018 10:12:30 -0800 (PST) From: Andrey Smirnov To: linux-kernel@vger.kernel.org Cc: Andrey Smirnov , bhelgaas@google.com, Fabio Estevam , cphealy@gmail.com, l.stach@pengutronix.de, Leonard Crestez , "A.s. Dong" , Richard Zhu , linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org Subject: [PATCH 0/3] PCIE support for i.MX8MQ Date: Sat, 17 Nov 2018 10:12:22 -0800 Message-Id: <20181117181225.10737-1-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Everyone: This series contains changes I made in order to enable support of PCIE IP block on i.MX8MQ SoCs (full tree can be found at [github-v0]). This series is _very_ preliminary and by no means is ready for inclusion (it also has some unmet dependencies). However is should be in OK enough shape to get some early feedback on, which is the intent of this submission. Specifically, I'd like to get some feedback on whether newly introduced "fsl,iomux-gpr1x" and "fsl,gpr12-device-type" DT properties, added to handle differences between PCIE0 and PCIE1, is a good (acceptable) solution for the problem. All other feedback is appreciated as well! Thank you, Andrey Smirnov [github-v0] https://github.com/ndreys/linux/commits/imx8mq-pcie-v0 Andrey Smirnov (3): PCI: imx: No-op imx6_setup_phy_mpll() on i.MX7D PCI: imx: No-op imx6_pcie_reset_phy() on i.MX7D PCI: imx: Add support for i.MX8MQ drivers/pci/controller/dwc/Kconfig | 2 +- drivers/pci/controller/dwc/pci-imx6.c | 119 +++++++++++++++++++++++++- 2 files changed, 117 insertions(+), 4 deletions(-) -- 2.19.1