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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id 64sm503850pff.101.2018.11.17.15.10.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 17 Nov 2018 15:10:49 -0800 (PST) Date: Sat, 17 Nov 2018 15:10:47 -0800 From: Bjorn Andersson To: Vinod Koul Cc: Andy Gross , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v5 01/18] arm64: dts: qcom: qcs404: add base dts files Message-ID: <20181117231047.GA2225@minitux> References: <20181109094417.12109-1-vkoul@kernel.org> <20181109094417.12109-2-vkoul@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181109094417.12109-2-vkoul@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri 09 Nov 01:44 PST 2018, Vinod Koul wrote: > Add base dts files for QCS404 chipset along with cpu, timer, > gcc and uart2 nodes. > > Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > arch/arm64/boot/dts/qcom/qcs404.dtsi | 175 +++++++++++++++++++++++++++++++++++ > 1 file changed, 175 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qcs404.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi > new file mode 100644 > index 000000000000..91abcdc78505 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi > @@ -0,0 +1,175 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (c) 2018, Linaro Limited > + > +#include > +#include > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + chosen { }; > + > + clocks { > + xo_board: xo-board { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <19200000>; > + }; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + CPU0: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x100>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + }; > + > + CPU1: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x101>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + }; > + > + CPU2: cpu@102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x102>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + }; > + > + CPU3: cpu@103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x103>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + }; > + > + L2_0: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + }; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + /* We expect the bootloader to fill in the size */ > + reg = <0 0x80000000 0 0>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + soc: soc@0 { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0 0xffffffff>; > + compatible = "simple-bus"; > + > + gcc: clock-controller@1800000 { > + compatible = "qcom,gcc-qcs404"; > + reg = <0x01800000 0x80000>; > + #clock-cells = <1>; > + > + assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; > + assigned-clock-rates = <19200000>; > + }; > + > + blsp1_uart2: serial@78b1000 { > + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; > + reg = <0x078b1000 0x200>; > + interrupts = ; > + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; > + clock-names = "core", "iface"; > + status = "okay"; > + }; > + > + intc: interrupt-controller@b000000 { > + compatible = "qcom,msm-qgic2"; > + interrupt-controller; > + #interrupt-cells = <3>; > + reg = <0x0b000000 0x1000>, > + <0x0b002000 0x1000>; > + }; > + > + timer@b120000 { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + compatible = "arm,armv7-timer-mem"; > + reg = <0x0b120000 0x1000>; > + clock-frequency = <19200000>; > + > + frame@b121000 { > + frame-number = <0>; > + interrupts = , > + ; > + reg = <0x0b121000 0x1000>, > + <0x0b122000 0x1000>; > + }; > + > + frame@b123000 { > + frame-number = <1>; > + interrupts = ; > + reg = <0x0b123000 0x1000>; > + status = "disabled"; > + }; > + > + frame@b124000 { > + frame-number = <2>; > + interrupts = ; > + reg = <0x0b124000 0x1000>; > + status = "disabled"; > + }; > + > + frame@b125000 { > + frame-number = <3>; > + interrupts = ; > + reg = <0x0b125000 0x1000>; > + status = "disabled"; > + }; > + > + frame@b126000 { > + frame-number = <4>; > + interrupts = ; > + reg = <0x0b126000 0x1000>; > + status = "disabled"; > + }; > + > + frame@b127000 { > + frame-number = <5>; > + interrupts = ; > + reg = <0xb127000 0x1000>; > + status = "disabled"; > + }; > + > + frame@b128000 { > + frame-number = <6>; > + interrupts = ; > + reg = <0x0b128000 0x1000>; > + status = "disabled"; > + }; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + }; > +}; > -- > 2.14.4 >