From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Masami Hiramatsu <masami.hiramatsu@linaro.org>,
Jassi Brar <jaswinder.singh@linaro.org>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Subject: Re: [RESEND PATCH v3 1/2] dt-bindings: PCI: Add UniPhier PCIe host controller description
Date: Mon, 19 Nov 2018 11:40:36 +0000 [thread overview]
Message-ID: <20181119114028.GA30042@e107981-ln.cambridge.arm.com> (raw)
In-Reply-To: <1539667641-26024-2-git-send-email-hayashi.kunihiko@socionext.com>
On Tue, Oct 16, 2018 at 02:27:20PM +0900, Kunihiko Hayashi wrote:
> Add DT bindings for PCIe controller implemented in UniPhier SoCs when
> configured in Root Complex (host) mode. This controller is based on
> the DesignWare PCIe core.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> .../devicetree/bindings/pci/uniphier-pcie.txt | 81 ++++++++++++++++++++++
> 1 file changed, 81 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/uniphier-pcie.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt
> new file mode 100644
> index 0000000..46a2754
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt
> @@ -0,0 +1,81 @@
> +Socionext UniPhier PCIe host controller bindings
> +
> +This describes the devicetree bindings for PCIe host controller implemented
> +on Socionext UniPhier SoCs.
> +
> +UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
> +It shares common functions with the PCIe DesignWare core driver and inherits
> +common properties defined in
> +Documentation/devicetree/bindings/pci/designware-pcie.txt.
> +
> +Required properties:
> +- compatible: Should be "socionext,uniphier-pcie".
> +- reg: Specifies offset and length of the register set for the device.
> + According to the reg-names, appropriate register sets are required.
> +- reg-names: Must include the following entries:
> + "dbi" - controller configuration registers
> + "link" - SoC-specific glue layer registers
> + "config" - PCIe configuration space
> +- clocks: A phandle to the clock gate for PCIe glue layer including
> + the host controller.
> +- resets: A phandle to the reset line for PCIe glue layer including
> + the host controller.
> +- interrupts: A list of interrupt specifiers. According to the
> + interrupt-names, appropriate interrupts are required.
> +- interrupt-names: Must include the following entries:
> + "dma" - DMA interrupt
> + "msi" - MSI interrupt
> +
> +Optional properties:
> +- phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate
> + phys are required.
> +- phy-names: Must be "pcie-phy".
> +
> +Required sub-node:
> +- legacy-interrupt-controller: Specifies interrupt controller for legacy PCI
> + interrupts.
> +
> +Required properties for legacy-interrupt-controller:
> +- interrupt-controller: identifies the node as an interrupt controller.
> +- #interrupt-cells: specifies the number of cells needed to encode an
> + interrupt source. The value must be 1.
> +- interrupt-parent: Phandle to the parent interrupt controller.
> +- interrupts: An interrupt specifier for legacy interrupt.
> +
> +Example:
> +
> + pcie: pcie@66000000 {
> + compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
> + status = "disabled";
> + reg-names = "dbi", "link", "config";
> + reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
> + <0x2fff0000 0x10000>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + clocks = <&sys_clk 24>;
> + resets = <&sys_rst 24>;
> + num-lanes = <1>;
> + num-viewport = <1>;
> + bus-range = <0x0 0xff>;
> + device_type = "pci";
> + ranges =
> + /* downstream I/O */
> + <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000
> + /* non-prefetchable memory */
> + 0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
> + #interrupt-cells = <1>;
> + interrupt-names = "dma", "msi";
> + interrupts = <0 224 4>, <0 225 4>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc 1>, /* INTA */
> + <0 0 0 2 &pcie_intc 2>, /* INTB */
> + <0 0 0 3 &pcie_intc 3>, /* INTC */
> + <0 0 0 4 &pcie_intc 4>; /* INTD */
This is not correct and we must fix this concept for all DWC based host
bridges bindings. We are mapping INTX to inputs [0,1,2,3] of the host
bridge interrupt controllers and the binding should reflect that.
This should be the correct mapping:
interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
<0 0 0 2 &pcie_intc 1>, /* INTB */
<0 0 0 3 &pcie_intc 2>, /* INTC */
<0 0 0 4 &pcie_intc 3>; /* INTD */
Lorenzo
> +
> + pcie_intc: legacy-interrupt-controller {
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 226 4>;
> + };
> + };
> --
> 2.7.4
>
next prev parent reply other threads:[~2018-11-19 11:40 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-16 5:27 [RESEND PATCH v3 0/2] add new UniPhier PCIe host driver Kunihiko Hayashi
2018-10-16 5:27 ` [RESEND PATCH v3 1/2] dt-bindings: PCI: Add UniPhier PCIe host controller description Kunihiko Hayashi
2018-11-19 11:40 ` Lorenzo Pieralisi [this message]
2018-11-20 12:15 ` Kunihiko Hayashi
2018-10-16 5:27 ` [RESEND PATCH v3 2/2] PCI: uniphier: Add UniPhier PCIe host controller support Kunihiko Hayashi
2018-11-19 16:17 ` Lorenzo Pieralisi
2018-11-20 12:15 ` Kunihiko Hayashi
2018-11-23 17:50 ` Lorenzo Pieralisi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181119114028.GA30042@e107981-ln.cambridge.arm.com \
--to=lorenzo.pieralisi@arm.com \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=gustavo.pimentel@synopsys.com \
--cc=hayashi.kunihiko@socionext.com \
--cc=jaswinder.singh@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=masami.hiramatsu@linaro.org \
--cc=robh+dt@kernel.org \
--cc=yamada.masahiro@socionext.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).