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Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv2 22/25] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Thread-Topic: [PATCHv2 22/25] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Thread-Index: AQHUgLNPczhc2hMl6EuKyPkcknZC0A== Date: Tue, 20 Nov 2018 09:27:51 +0000 Message-ID: <20181120092615.11680-23-Zhiqiang.Hou@nxp.com> References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0050.apcprd03.prod.outlook.com (2603:1096:202:17::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;AM6PR04MB4775;6:4fR1Phc9/JNPoLtakd3OiUtHW8C/02MwltS0CbkbHN1f5WSTyPfIANa97MnwzS8yDo5i54/bRbJFB4zXXd+5dWZnzNP/Hm54u55lWATjeMRQZIlUxFiyNrq17ATr07g6WHPe2ghP1AEo5NqzhuugvaBdqV68ZYb1MdS1caOZieuEuZN8cjRuSpJcL9w7DRGAV0b+v2U7hURfvXEh2WIw4TBRmQwzK4EYfNCNEBXecCZpBYE3M8eUPHYu3KlkvMtzLlc/7X2fPhgF1qB2VL6rvBfTdE9IXOZLVEMUGlVWtgZdfzL8yIzq9TS5hq/uBu2W6s/FWqwyPrTxaDFgCk6jUi5qk6oi4dJqUlDvZ6LDgyabZT1FYUlFPJJicGe4KdEVHyyMQFukNEXwHbE7734ShETAMQ15tB0AK8h8XewgJFP+f2T4S75H8wQX04HBjfP4zDGHV1O4ncQqoJKND+m1WA==;5:us0F8gc3ILlxMx5rKU7M/+Ydg0SP7n2sMssA6OeRIqxuN8kIaTkidO6IrP3e170f+4YV/YTv/ha2apkOc4XIGCj40FkPk65VK7yodfsYJKzekq7xiXBqVl/p7WLFf5yhHyv0KhOtzC/g9x/IfmXdKYzCWXvOs2wQ7uQtv15kJtA=;7:RSidDyI37FtulDCoUm3ZyHoN+ABcEzq4kE1dlQ+aahr5lI9J4x+DA3p2QgbLTEvV9QsDXfx/LhJBmcoKi5lkDC+e/7IP4p1mWQLb0bFIm3dZ/Zjc8PC7ceh0I9xWXrds3VcXcp1tIA45cB6rnO5eyg== x-ms-office365-filtering-correlation-id: 08048503-fd52-4f92-690a-08d64eca7180 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020);SRVR:AM6PR04MB4775; x-ms-traffictypediagnostic: AM6PR04MB4775: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(3231442)(944501410)(52105112)(3002001)(10201501046)(6055026)(148016)(149066)(150057)(6041310)(20161123562045)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095);SRVR:AM6PR04MB4775;BCL:0;PCL:0;RULEID:;SRVR:AM6PR04MB4775; x-forefront-prvs: 08626BE3A5 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6029001)(366004)(39860400002)(136003)(376002)(396003)(346002)(189003)(199004)(66066001)(1076002)(2900100001)(68736007)(8676002)(6486002)(5660300001)(8936002)(6116002)(3846002)(2501003)(97736004)(81166006)(26005)(186003)(81156014)(105586002)(7416002)(102836004)(2906002)(386003)(6506007)(7736002)(305945005)(106356001)(6512007)(76176011)(36756003)(4326008)(99286004)(52116002)(25786009)(575784001)(110136005)(54906003)(2616005)(86362001)(53936002)(446003)(11346002)(256004)(2201001)(6436002)(486006)(71190400001)(71200400001)(478600001)(316002)(476003)(14454004)(921003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:AM6PR04MB4775;H:AM6PR04MB5781.eurprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: cjj/+wth+ycJM5PEbmwekiUmGl79nzeanlzytY/1yxNDuOnVElmBXJ7ybrW8cNxISoYS3lcU4FdmCaUOOjPDu1IawPjGrncJOgUyhnNg01+fwZTTBBsNFCw3fK6qdwEcc2dv6v4jD+R8hqBdjx2NdnoyONAbXKq9T1FAF7r7fAwzx9WD7aX/lDLl7afsWS/NntjAiyvKKpgeJ1WDudtRcL5bBFFwIfYia2ZahfzNuhs/Umkcxknu1KzUsD1EWgntooj5010R+H3BJk0vuBfZXsx4S1xETm3iaIfAX/2K9i8GDpPdBkYuDI1oz9k2qVeyrrcrooh5XfoMAimztdiVwuhVz9eEQDusniBbrytVrJI= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 08048503-fd52-4f92-690a-08d64eca7180 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 09:27:51.6605 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4775 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Hou Zhiqiang Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs. Signed-off-by: Hou Zhiqiang --- V2: - Change to use the layerscape-pci.txt for PCIe Gen4 controller dt-bindings .../bindings/pci/layerscape-pci.txt | 57 +++++++++++++++++++ MAINTAINERS | 8 +++ 2 files changed, 65 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Doc= umentation/devicetree/bindings/pci/layerscape-pci.txt index 66df1e81e0b8..3ef8836b6e97 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -1,4 +1,6 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Freescale Layerscape PCIe controller +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in designware-pcie.txt= . @@ -58,3 +60,58 @@ Example: <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; }; + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +NXP Layerscape PCIe Gen4 controller +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This PCIe controller is based on the Mobiveil PCIe IP and thus inherits al= l +the common properties defined in mobiveil-pcie.txt. + +Required properties: +- compatible: should contain the platform identifier such as: + "fsl,lx2160a-pcie" +- reg: base addresses and lengths of the PCIe controller register blocks. + "config_axi_slave": PCIe controller registers + "csr_axi_slave": Bridge config registers +- interrupts: A list of interrupt outputs of the controller. Must contain = an + entry for each entry in the interrupt-names property. +- interrupt-names: It could include the following entries: + "intr": The interrupt that is asserted for controller interrupts + "aer": Asserted for aer interrupt when chip support the aer interrupt wi= th + none MSI/MSI-X/INTx mode,but there is interrupt line for aer. + "pme": Asserted for pme interrupt when chip support the pme interrupt wi= th + none MSI/MSI-X/INTx mode,but there is interrupt line for pme. +- dma-coherent: Indicates that the hardware IP block can ensure the cohere= ncy + of the data transferred from/to the IP block. This can avoid the softwar= e + cache flush/invalid actions, and improve the performance significantly. +- msi-parent : See the generic MSI binding described in + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + +Example: + + pcie@3400000 { + compatible =3D "fsl,lx2160a-pcie"; + reg =3D <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names =3D "csr_axi_slave", "config_axi_slave"; + interrupts =3D , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names =3D "aer", "pme", "intr"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + apio-wins =3D <8>; + ppio-wins =3D <8>; + dma-coherent; + bus-range =3D <0x0 0xff>; + msi-parent =3D <&its>; + ranges =3D <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 084d225583e0..b59763e23392 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11405,6 +11405,14 @@ L: linux-arm-kernel@lists.infradead.org S: Maintained F: drivers/pci/controller/dwc/*layerscape* =20 +PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER +M: Hou Zhiqiang +L: linux-pci@vger.kernel.org +L: linux-arm-kernel@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/pci/layerscape-pci.txt +F: drivers/pci/controller/mobibeil/pci-layerscape-gen4.c + PCI DRIVER FOR GENERIC OF HOSTS M: Will Deacon L: linux-pci@vger.kernel.org --=20 2.17.1