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[46.139.12.213]) by smtp.gmail.com with ESMTPSA id e16sm354312wrn.72.2018.11.26.05.30.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Nov 2018 05:30:46 -0800 (PST) Date: Mon, 26 Nov 2018 14:30:43 +0100 From: Ingo Molnar To: Thomas Gleixner Cc: Linus Torvalds , Linux List Kernel Mailing , the arch/x86 maintainers , Peter Zijlstra , Andrew Lutomirski , Jiri Kosina , thomas.lendacky@amd.com, Josh Poimboeuf , Andrea Arcangeli , David Woodhouse , Tim Chen , Andi Kleen , dave.hansen@intel.com, Casey Schaufler , "Mallick, Asit K" , "Van De Ven, Arjan" , jcm@redhat.com, longman9394@gmail.com, Greg KH , david.c.stewart@intel.com, Kees Cook Subject: Re: [patch V2 27/28] x86/speculation: Add seccomp Spectre v2 user space protection mode Message-ID: <20181126133043.GA108014@gmail.com> References: <20181125183328.318175777@linutronix.de> <20181125185006.051663132@linutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Thomas Gleixner wrote: > On Sun, 25 Nov 2018, Linus Torvalds wrote: > > > [ You forgot to fix your quilt setup.. ] > > Duh. Should have pinned that package. > > > On Sun, 25 Nov 2018, Thomas Gleixner wrote: > > > > > > The mitigation guide documents how STIPB works: > > > > > > Setting bit 1 (STIBP) of the IA32_SPEC_CTRL MSR on a logical processor > > > prevents the predicted targets of indirect branches on any logical > > > processor of that core from being controlled by software that executes > > > (or executed previously) on another logical processor of the same core. > > > > Can we please just fix this stupid lie? > > Well, it's not a lie. The above is correct, it just does not tell WHY this > works. Well, it's a "technically correct but misleading" phrase, which has much more of the effects of an actual "lie" than that of a true description of it. I.e. in terms of what effects it's likely going to have on readers not aware of the underlying mechanics it's much more correct to call it a "lie" than to call it "truth" - which I think is at the core of Linus's argument. > > Yes, Intel calls it "STIBP" and tries to make it out to be about the > > indirect branch predictor being per-SMT thread. > > > > But the reason it is unacceptable is apparently because in reality it > > just disables indirect branch prediction entirely. So yes, > > *technically* it's true that that limits indirect branch prediction > > to just a single SMT core, but in reality it is just a "go really > > slow" mode. > > Indeed. Just checked the documentation again, it's also not clear > whether IBPB is required if STIPB is in use. So I think we should clarify all this. Thanks, Ingo