From: Boris Brezillon <boris.brezillon@bootlin.com>
To: vitor <vitor.soares@synopsys.com>
Cc: <wsa@the-dreams.de>, <linux-i2c@vger.kernel.org>,
<corbet@lwn.net>, <linux-doc@vger.kernel.org>,
<gregkh@linuxfoundation.org>, <arnd@arndb.de>,
<psroka@cadence.com>, <agolec@cadence.com>,
<adouglas@cadence.com>, <bfolta@cadence.com>, <dkos@cadence.com>,
<alicja@cadence.com>, <cwronka@cadence.com>,
<sureshp@cadence.com>, <rafalc@cadence.com>,
<thomas.petazzoni@bootlin.com>, <nm@ti.com>, <robh+dt@kernel.org>,
<pawel.moll@arm.com>, <mark.rutland@arm.com>,
<ijc+devicetree@hellion.org.uk>, <galak@codeaurora.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<geert@linux-m68k.org>, <linus.walleij@linaro.org>,
<Xiang.Lin@synaptics.com>, <linux-gpio@vger.kernel.org>,
<nsekhar@ti.com>, <pgaj@cadence.com>, <peda@axentia.se>,
<mshettel@codeaurora.org>, <swboyd@chromium.org>,
<joao.pinto@synopsys.com>
Subject: Re: [PATCH] i3c: master: dw: split dw-i3c-master.c into master and bus specific parts
Date: Mon, 26 Nov 2018 21:06:38 +0100 [thread overview]
Message-ID: <20181126210638.0b8c4ee8@bbrezillon> (raw)
In-Reply-To: <b7f59793-aaaa-95ff-fe7d-943e558f65b5@synopsys.com>
On Mon, 26 Nov 2018 19:28:02 +0000
vitor <vitor.soares@synopsys.com> wrote:
> On 26/11/18 19:08, Boris Brezillon wrote:
> > On Mon, 26 Nov 2018 19:56:18 +0100
> > Boris Brezillon <boris.brezillon@bootlin.com> wrote:
> >
> >>> - for the others it will easy the SoC integration avoiding
> >>> duplicated work and doing things from scratch.
> >> What would be duplicated? You want to support a new SoC, just add a new
> >> entry in the of_match_table and you're done. When you need to add
> >> SoC/integration specific stuff, create a struct and attach a different
> >> instance per-compatible so that each SoC can have its own configuration
> >> (or even init sequence if needed). That's how we do for pretty much all
> >> IPs out there, why should designware ones be different?
> > To be more specific, I'd like a real example that shows why the
> > separation is needed.
>
> Ok no problem. We can delay this for PCI and other rules support.
I finally understand what this separation is all about: supporting both
PCI and platform devices. I guess I've been distracted by this sentence:
"
This patch will allow SOC integrators to add their code specific to
DesignWare I3C IP.
"
which for me meant each SoC would have its own platform_driver.
In any case, I think this is a bit premature do this separation, unless
you already know about one integrator planning to expose this IP over
PCI.
next prev parent reply other threads:[~2018-11-26 20:07 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-22 17:54 [PATCH] i3c: master: dw: split dw-i3c-master.c into master and bus specific parts Vitor Soares
2018-11-22 20:02 ` Boris Brezillon
2018-11-23 12:39 ` vitor
2018-11-23 12:50 ` Boris Brezillon
2018-11-26 12:06 ` vitor
2018-11-26 12:35 ` Boris Brezillon
2018-11-26 18:33 ` vitor
2018-11-26 18:56 ` Boris Brezillon
2018-11-26 19:08 ` Boris Brezillon
2018-11-26 19:28 ` vitor
2018-11-26 20:06 ` Boris Brezillon [this message]
2018-11-26 20:11 ` vitor
2018-11-26 21:33 ` Boris Brezillon
2018-11-27 11:50 ` vitor
2018-11-27 12:33 ` Boris Brezillon
2018-12-04 0:34 ` vitor
2018-12-04 9:19 ` Boris Brezillon
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