From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A33DEC04EBA for ; Tue, 27 Nov 2018 03:44:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 770152086B for ; Tue, 27 Nov 2018 03:44:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 770152086B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728453AbeK0Oju (ORCPT ); Tue, 27 Nov 2018 09:39:50 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:32095 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727571AbeK0Oju (ORCPT ); Tue, 27 Nov 2018 09:39:50 -0500 X-UUID: ecb06997c79d4610bda36922577510f3-20181127 X-UUID: ecb06997c79d4610bda36922577510f3-20181127 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 654770675; Tue, 27 Nov 2018 11:43:04 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 27 Nov 2018 11:43:01 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 27 Nov 2018 11:43:01 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Stephen Boyd , Rob Herring CC: James Liao , Fan Chen , , , , , , Weiyi Lu , Owen Chen Subject: [PATCH v2 02/11] clk: mediatek: add new member to mtk_pll_data Date: Tue, 27 Nov 2018 11:42:45 +0800 Message-ID: <20181127034254.24721-4-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181127034254.24721-1-weiyi.lu@mediatek.com> References: <20181127034254.24721-1-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 9FAAF7E71535DCF803CDCA98407C255470C814B54773BE1AD5EA70EC2AF929182000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Owen Chen 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits, add a variable to indicate this change and backward-compatible. 2. fmin: The pll freqency lower-bound is vary from 1GMhz to 1.5Ghz, add a variable to indicate platform-dependent. Signed-off-by: Owen Chen Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-mtk.h | 2 ++ drivers/clk/mediatek/clk-pll.c | 12 +++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f83c2bbb677e..11b5517903d0 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -214,8 +214,10 @@ struct mtk_pll_data { unsigned int flags; const struct clk_ops *ops; u32 rst_bar_mask; + unsigned long fmin; unsigned long fmax; int pcwbits; + int pcwibits; uint32_t pcw_reg; int pcw_shift; const struct mtk_pll_div_table *div_table; diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index f54e4015b0b1..1db161aced31 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -32,6 +32,8 @@ #define AUDPLL_TUNER_EN BIT(31) #define POSTDIV_MASK 0x7 + +/* default 7 bits integer, can be overridden with pcwibits. */ #define INTEGER_BITS 7 /* @@ -69,11 +71,13 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, { int pcwbits = pll->data->pcwbits; int pcwfbits; + int ibits; u64 vco; u8 c = 0; /* The fractional part of the PLL divider. */ - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; + pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0; vco = (u64)fin * pcw; @@ -138,9 +142,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, u32 freq, u32 fin) { - unsigned long fmin = 1000 * MHZ; + unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ); const struct mtk_pll_div_table *div_table = pll->data->div_table; u64 _pcw; + int ibits; u32 val; if (freq > pll->data->fmax) @@ -164,7 +169,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, } /* _pcw = freq * postdiv / fin * 2^pcwfbits */ - _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS); + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; + _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits); do_div(_pcw, fin); *pcw = (u32)_pcw; -- 2.18.0