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[82.243.161.21]) by smtp.googlemail.com with ESMTPSA id d4sm2721909wrp.89.2018.11.29.08.45.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 29 Nov 2018 08:45:33 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Carlo Caione , Kevin Hilman Cc: Jerome Brunet , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] dt-bindings: clk: meson: add main controller clock input Date: Thu, 29 Nov 2018 17:45:23 +0100 Message-Id: <20181129164524.18670-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181129164524.18670-1-jbrunet@baylibre.com> References: <20181129164524.18670-1-jbrunet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the clock input of the main clock controller Signed-off-by: Jerome Brunet --- Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e950599566a9..79454869f96d 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -9,6 +9,8 @@ Required Properties: "amlogic,gxbb-clkc" for GXBB SoC, "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. +- clocks: phandle to the input clock of the controller, presumably the + platform xtal. - #clock-cells: should be 1. @@ -31,6 +33,7 @@ sysctrl: system-controller@0 { clkc: clock-controller { #clock-cells = <1>; compatible = "amlogic,gxbb-clkc"; + clocks = <&xtal> }; }; -- 2.19.1