From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36A35C04EB8 for ; Tue, 4 Dec 2018 14:23:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 08450206B7 for ; Tue, 4 Dec 2018 14:23:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 08450206B7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726797AbeLDOXe (ORCPT ); Tue, 4 Dec 2018 09:23:34 -0500 Received: from mail.bootlin.com ([62.4.15.54]:33430 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726744AbeLDOXa (ORCPT ); Tue, 4 Dec 2018 09:23:30 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 1BD0620EDC; Tue, 4 Dec 2018 15:23:26 +0100 (CET) Received: from localhost.localdomain (aaubervilliers-681-1-79-44.w90-88.abo.wanadoo.fr [90.88.21.44]) by mail.bootlin.com (Postfix) with ESMTPSA id C7BCA20E29; Tue, 4 Dec 2018 15:22:43 +0100 (CET) From: Paul Kocialkowski To: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Maxime Ripard , David Airlie , Chen-Yu Tsai , Maarten Lankhorst , Sean Paul , Thomas Petazzoni , linux-sunxi@googlegroups.com, Daniel Vetter , Paul Kocialkowski Subject: [PATCH v3 20/21] drm/sun4i: frontend: Move the FIR filter phases to our quirks Date: Tue, 4 Dec 2018 15:22:17 +0100 Message-Id: <20181204142218.16284-21-paul.kocialkowski@bootlin.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204142218.16284-1-paul.kocialkowski@bootlin.com> References: <20181204142218.16284-1-paul.kocialkowski@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Maxime Ripard The FIR filters phase depend on the SoC, so let's move it to our quirks structure instead of removing them. Signed-off-by: Maxime Ripard Signed-off-by: Paul Kocialkowski --- drivers/gpu/drm/sun4i/sun4i_frontend.c | 28 ++++++++++++++++++++------ drivers/gpu/drm/sun4i/sun4i_frontend.h | 5 +++++ 2 files changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_frontend.c b/drivers/gpu/drm/sun4i/sun4i_frontend.c index da1bb82d534e..d17394a367b3 100644 --- a/drivers/gpu/drm/sun4i/sun4i_frontend.c +++ b/drivers/gpu/drm/sun4i/sun4i_frontend.c @@ -448,12 +448,18 @@ int sun4i_frontend_update_formats(struct sun4i_frontend *frontend, * I have no idea what this does exactly, but it seems to be * related to the scaler FIR filter phase parameters. */ - regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZPHASE_REG, 0x400); - regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZPHASE_REG, 0x400); - regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE0_REG, 0x400); - regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE0_REG, 0x400); - regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE1_REG, 0x400); - regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE1_REG, 0x400); + regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZPHASE_REG, + frontend->data->ch_phase[0].horzphase); + regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZPHASE_REG, + frontend->data->ch_phase[1].horzphase); + regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE0_REG, + frontend->data->ch_phase[0].vertphase[0]); + regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE0_REG, + frontend->data->ch_phase[1].vertphase[0]); + regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE1_REG, + frontend->data->ch_phase[0].vertphase[1]); + regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE1_REG, + frontend->data->ch_phase[1].vertphase[1]); /* * Checking the input format is sufficient since we currently only @@ -687,6 +693,16 @@ static const struct dev_pm_ops sun4i_frontend_pm_ops = { }; static const struct sun4i_frontend_data sun8i_a33_frontend = { + .ch_phase = { + { + .horzphase = 0x400, + .vertphase = { 0x400, 0x400 }, + }, + { + .horzphase = 0x400, + .vertphase = { 0x400, 0x400 }, + }, + }, .has_coef_access_ctrl = true, }; diff --git a/drivers/gpu/drm/sun4i/sun4i_frontend.h b/drivers/gpu/drm/sun4i/sun4i_frontend.h index 458a5e69f56f..14963b7cf051 100644 --- a/drivers/gpu/drm/sun4i/sun4i_frontend.h +++ b/drivers/gpu/drm/sun4i/sun4i_frontend.h @@ -104,6 +104,11 @@ struct reset_control; struct sun4i_frontend_data { bool has_coef_access_ctrl; bool has_coef_rdy; + + struct { + u32 horzphase; + u32 vertphase[2]; + } ch_phase[2]; }; struct sun4i_frontend { -- 2.19.2