Re: [RFC AFBC 08/12] drm/arm/malidp: Specified the rotation memory requirements for AFBC YUV formats

[Liviu Dudau <Liviu.Dudau@arm.com>]

On Mon, Dec 03, 2018 at 11:32:02AM +0000, Ayan Halder wrote:
> The newly supported AFBC YUV formats have the following rotation memory
> constraints (in DP550/DP650).
> 1. DRM_FORMAT_VUY888/DRM_FORMAT_VUY101010 :- It can rotate upto 8
> horizontal lines in the AFBC output buffer.
> 2. DRM_FORMAT_YUV420_8BIT :- It can rotate upto 16 horizontal lines
> in the AFBC output buffer.
> 
> Also some of the pixel formats are specified in bits per pixel (rather
> than bytes per pixel), so the calculation needs to take note of this.
> 
> Besides there are some difference between DP550 and DP650 and these are
> as follows:-
> 1. DRM_FORMAT_X0L2 (in uncompressed format) does not support rotation in DP550.
> For DP650, it can rotate upto 16 horizontal lines in the AFBC output buffer,
> whereas in DP550 (with AFBC), it can rotate upto 8 horizontal lines.
> 2. DRM_FORMAT_YUV420_10BIT :- It can rotate upto 8 horizontal lines in
> dp550 and 16 horizontal lines in DP650.
> 
> Signed-off-by: Ayan Kumar halder <ayan.halder@arm.com>

Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>

Best regards,
Liviu

> ---
>  drivers/gpu/drm/arm/malidp_hw.c     | 101 ++++++++++++++++++++++++++++++++----
>  drivers/gpu/drm/arm/malidp_hw.h     |   5 +-
>  drivers/gpu/drm/arm/malidp_planes.c |   3 +-
>  3 files changed, 98 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c
> index 4a774be..d9866a8 100644
> --- a/drivers/gpu/drm/arm/malidp_hw.c
> +++ b/drivers/gpu/drm/arm/malidp_hw.c
> @@ -375,14 +375,39 @@ static void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode *
>  		malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
>  }
>  
> -static int malidp500_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt)
> +int malidp_format_get_bpp(u32 fmt)
> +{
> +	int bpp = drm_format_plane_cpp(fmt, 0) * 8;
> +
> +	if (bpp == 0) {
> +		switch (fmt) {
> +		case DRM_FORMAT_VUY101010:
> +			bpp = 30;
> +		case DRM_FORMAT_YUV420_10BIT:
> +			bpp = 15;
> +			break;
> +		case DRM_FORMAT_YUV420_8BIT:
> +			bpp = 12;
> +			break;
> +		default:
> +			bpp = 0;
> +		}
> +	}
> +
> +	return bpp;
> +}
> +
> +static int malidp500_rotmem_required(struct malidp_hw_device *hwdev, u16 w,
> +				     u16 h, u32 fmt, bool has_modifier)
>  {
>  	/*
>  	 * Each layer needs enough rotation memory to fit 8 lines
>  	 * worth of pixel data. Required size is then:
>  	 *    size = rotated_width * (bpp / 8) * 8;
>  	 */
> -	return w * drm_format_plane_cpp(fmt, 0) * 8;
> +	int bpp = malidp_format_get_bpp(fmt);
> +
> +	return w * bpp;
>  }
>  
>  static void malidp500_se_write_pp_coefftab(struct malidp_hw_device *hwdev,
> @@ -660,9 +685,9 @@ static void malidp550_modeset(struct malidp_hw_device *hwdev, struct videomode *
>  		malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
>  }
>  
> -static int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt)
> +static int malidpx50_get_bytes_per_column(u32 fmt)
>  {
> -	u32 bytes_per_col;
> +	u32 bytes_per_column;
>  
>  	switch (fmt) {
>  	/* 8 lines at 4 bytes per pixel */
> @@ -688,19 +713,77 @@ static int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_YUYV:
>  	case DRM_FORMAT_X0L0:
> -	case DRM_FORMAT_X0L2:
> -		bytes_per_col = 32;
> +		bytes_per_column = 32;
>  		break;
>  	/* 16 lines at 1.5 bytes per pixel */
>  	case DRM_FORMAT_NV12:
>  	case DRM_FORMAT_YUV420:
> -		bytes_per_col = 24;
> +	/* 8 lines at 3 bytes per pixel */
> +	case DRM_FORMAT_VUY888:
> +	/* 16 lines at 12 bits per pixel */
> +	case DRM_FORMAT_YUV420_8BIT:
> +	/* 8 lines at 3 bytes per pixel */
> +	case DRM_FORMAT_P010:
> +		bytes_per_column = 24;
> +		break;
> +	/* 8 lines at 30 bits per pixel */
> +	case DRM_FORMAT_VUY101010:
> +	/* 16 lines at 15 bits per pixel */
> +	case DRM_FORMAT_YUV420_10BIT:
> +		bytes_per_column = 30;
>  		break;
>  	default:
>  		return -EINVAL;
>  	}
>  
> -	return w * bytes_per_col;
> +	return bytes_per_column;
> +}
> +
> +static int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w,
> +				     u16 h, u32 fmt, bool has_modifier)
> +{
> +	int bytes_per_column = 0;
> +
> +	switch (fmt) {
> +	/* 8 lines at 15 bits per pixel */
> +	case DRM_FORMAT_YUV420_10BIT:
> +		bytes_per_column = 15;
> +		break;
> +	/* Uncompressed YUV 420 10 bit single plane cannot be rotated */
> +	case DRM_FORMAT_X0L2:
> +		if (has_modifier)
> +			bytes_per_column = 8;
> +		else
> +			return -EINVAL;
> +		break;
> +	default:
> +		bytes_per_column = malidpx50_get_bytes_per_column(fmt);
> +	}
> +
> +	if (bytes_per_column == -EINVAL)
> +		return bytes_per_column;
> +
> +	return w * bytes_per_column;
> +}
> +
> +static int malidp650_rotmem_required(struct malidp_hw_device *hwdev, u16 w,
> +				     u16 h, u32 fmt, bool has_modifier)
> +{
> +	int bytes_per_column = 0;
> +
> +	switch (fmt) {
> +	/* 16 lines at 2 bytes per pixel */
> +	case DRM_FORMAT_X0L2:
> +		bytes_per_column = 32;
> +		break;
> +	default:
> +		bytes_per_column = malidpx50_get_bytes_per_column(fmt);
> +	}
> +
> +	if (bytes_per_column == -EINVAL)
> +		return bytes_per_column;
> +
> +	return w * bytes_per_column;
>  }
>  
>  static int malidp550_se_set_scaling_coeffs(struct malidp_hw_device *hwdev,
> @@ -979,7 +1062,7 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = {
>  		.in_config_mode = malidp550_in_config_mode,
>  		.set_config_valid = malidp550_set_config_valid,
>  		.modeset = malidp550_modeset,
> -		.rotmem_required = malidp550_rotmem_required,
> +		.rotmem_required = malidp650_rotmem_required,
>  		.se_set_scaling_coeffs = malidp550_se_set_scaling_coeffs,
>  		.se_calc_mclk = malidp550_se_calc_mclk,
>  		.enable_memwrite = malidp550_enable_memwrite,
> diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h
> index 52188f0..e89a06a 100644
> --- a/drivers/gpu/drm/arm/malidp_hw.h
> +++ b/drivers/gpu/drm/arm/malidp_hw.h
> @@ -184,7 +184,8 @@ struct malidp_hw {
>  	 * Calculate the required rotation memory given the active area
>  	 * and the buffer format.
>  	 */
> -	int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt);
> +	int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h,
> +			       u32 fmt, bool has_modifier);
>  
>  	int (*se_set_scaling_coeffs)(struct malidp_hw_device *hwdev,
>  				     struct malidp_se_config *se_config,
> @@ -326,6 +327,8 @@ void malidp_se_irq_fini(struct malidp_hw_device *hwdev);
>  u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
>  			   u8 layer_id, u32 format, bool has_modifier);
>  
> +int malidp_format_get_bpp(u32 fmt);
> +
>  static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated)
>  {
>  	/*
> diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c
> index 0765cee..d0a00ee 100644
> --- a/drivers/gpu/drm/arm/malidp_planes.c
> +++ b/drivers/gpu/drm/arm/malidp_planes.c
> @@ -595,7 +595,8 @@ static int malidp_de_plane_check(struct drm_plane *plane,
>  
>  		val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_w,
>  						     state->crtc_h,
> -						     fb->format->format);
> +						     fb->format->format,
> +						     !!(fb->modifier));
>  		if (val < 0)
>  			return val;
>  
> -- 
> 2.7.4
> 

-- 
====================
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| but they're not |
| giving me the   |
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