[PATCH v2 0/3] arm64: dts: qcom: sdm845: Add SD nodes

[PATCH v2 0/3] arm64: dts: qcom: sdm845: Add SD nodes

[Evan Green]

This series adds the nodes for one of the two SD host controllers on SDM845,
and wires it up on the MTP.

Though I tested similar changes on another board, I was unable to actually run
this on an MTP. If someone felt like trying this out on an MTP I would be
grateful.

The original downstream nodes had sleep pinctrl states. It's not obvious to
me that all this messing with drive-strength saves non-negligible amounts of
power, so I didn't add them and figured we could add them later if needed.

Changes in v2:
 - Reworded commit message to note that there are multiple SD
 controllers.
 - Fixed alphabetization of node placement in sdm845-mtp.dtsi (Doug)
 - Fixed card detect name to match schematics (Doug).
 - Moved comment about drive strength next to the drive-strength entry
 (Doug)
 - Removed drive-strength from card detect input pin (Doug).
 - Consolidated tlmm nodes in MTP.

Evan Green (3):
  dt-bindings: mmc: sdhci-msm: Clarify register requirements
  arm64: dts: qcom: sdm845: Add SD node
  arm64: dts: qcom: sdm845: Add SD nodes for sdm845-mtp

 .../devicetree/bindings/mmc/sdhci-msm.txt     |  2 +-
 arch/arm64/boot/dts/qcom/sdm845-mtp.dts       | 58 ++++++++++++++++++-
 arch/arm64/boot/dts/qcom/sdm845.dtsi          | 15 +++++
 3 files changed, 72 insertions(+), 3 deletions(-)

-- 
2.18.1

[PATCH v2 1/3] dt-bindings: mmc: sdhci-msm: Clarify register requirements

[Evan Green]

In sdhci-msm-v5 and beyond, the MCI registers are removed, so there is only
one register region required.

Signed-off-by: Evan Green <evgreen@chromium.org>
---

Changes in v2: None

 Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
index b72871ac90cb2..da4edb146a983 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
@@ -25,7 +25,7 @@ Required properties:
 
 - reg: Base address and length of the register in the following order:
 	- Host controller register map (required)
-	- SD Core register map (required)
+	- SD Core register map (required for msm-v4 and below)
 - interrupts: Should contain an interrupt-specifiers for the interrupts:
 	- Host controller interrupt (required)
 - pinctrl-names: Should contain only one value - "default".
-- 
2.18.1

[PATCH v2 2/3] arm64: dts: qcom: sdm845: Add SD node

[Evan Green]

Add one of the two SD controllers to SDM845.

Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---

Changes in v2:
 - Reworded commit message to note that there are multiple SD
 controllers.

 arch/arm64/boot/dts/qcom/sdm845.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 1419b0098cb38..bb8eacdf40910 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1078,6 +1078,21 @@
 			};
 		};
 
+		sdhc_2: sdhci@8804000 {
+			compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0x8804000 0x1000>;
+
+			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>;
+			clock-names = "iface", "core";
+
+			status = "disabled";
+		};
+
 		usb_1_hsphy: phy@88e2000 {
 			compatible = "qcom,sdm845-qusb2-phy";
 			reg = <0x88e2000 0x400>;
-- 
2.18.1

[PATCH v2 3/3] arm64: dts: qcom: sdm845: Add SD nodes for sdm845-mtp

[Evan Green]

Enable support for one of the micro SD slots on the MTP.

Signed-off-by: Evan Green <evgreen@chromium.org>
---

Changes in v2:
 - Fixed alphabetization of node placement in sdm845-mtp.dtsi (Doug)
 - Fixed card detect name to match schematics (Doug).
 - Moved comment about drive strength next to the drive-strength entry
 (Doug)
 - Removed drive-strength from card detect input pin (Doug).
 - Consolidated tlmm nodes in MTP.

 arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 58 ++++++++++++++++++++++++-
 1 file changed, 56 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index b3def03581775..cde76da42cbb7 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -7,6 +7,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "sdm845.dtsi"
 
@@ -358,8 +359,16 @@
 	status = "okay";
 };
 
-&tlmm {
-	gpio-reserved-ranges = <0 4>, <81 4>;
+&sdhc_2 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>;
+
+	vmmc-supply = <&vreg_l21a_2p95>;
+	vqmmc-supply = <&vddpx_2>;
+
+	cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
 };
 
 &uart9 {
@@ -450,3 +459,48 @@
 		bias-pull-up;
 	};
 };
+
+&tlmm {
+	gpio-reserved-ranges = <0 4>, <81 4>;
+
+	sdc2_clk: sdc2-clk {
+		pinconf {
+			pins = "sdc2_clk";
+			bias-disable;
+
+			/*
+			 * It seems that mmc_test reports errors if drive
+			 * strength is not 16 on clk, cmd, and data pins.
+			 */
+			drive-strength = <16>;
+		};
+	};
+
+	sdc2_cmd: sdc2-cmd {
+		pinconf {
+			pins = "sdc2_cmd";
+			bias-pull-up;
+			drive-strength = <16>;
+		};
+	};
+
+	sdc2_data: sdc2-data {
+		pinconf {
+			pins = "sdc2_data";
+			bias-pull-up;
+			drive-strength = <16>;
+		};
+	};
+
+	sd_card_det_n: sd-card-det-n {
+		pinmux {
+			pins = "gpio126";
+			function = "gpio";
+		};
+
+		pinconf {
+			pins = "gpio126";
+			bias-pull-up;
+		};
+	};
+};
-- 
2.18.1

Re: [PATCH v2 1/3] dt-bindings: mmc: sdhci-msm: Clarify register requirements

[Doug Anderson]

Hi,
On Thu, Dec 6, 2018 at 10:45 AM Evan Green <evgreen@chromium.org> wrote:
>
> In sdhci-msm-v5 and beyond, the MCI registers are removed, so there is only
> one register region required.
>
> Signed-off-by: Evan Green <evgreen@chromium.org>
> ---
>
> Changes in v2: None
>
>  Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

You probably should have skipped this patch from v2.  Ulf already
landed it.  It can be found at:

https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git/commit/?h=next&id=68fe87ac8a9309bbdc960cbd774725e44ea98b58

-Doug

Re: [PATCH v2 1/3] dt-bindings: mmc: sdhci-msm: Clarify register requirements

[Evan Green]

On Thu, Dec 6, 2018 at 3:34 PM Doug Anderson <dianders@chromium.org> wrote:
>
> Hi,
> On Thu, Dec 6, 2018 at 10:45 AM Evan Green <evgreen@chromium.org> wrote:
> >
> > In sdhci-msm-v5 and beyond, the MCI registers are removed, so there is only
> > one register region required.
> >
> > Signed-off-by: Evan Green <evgreen@chromium.org>
> > ---
> >
> > Changes in v2: None
> >
> >  Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
>
> You probably should have skipped this patch from v2.  Ulf already
> landed it.  It can be found at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git/commit/?h=next&id=68fe87ac8a9309bbdc960cbd774725e44ea98b58
>

Oh, oops. Ignore this 1/3 patch then, but the other two are valid.
-Evan

Re: [PATCH v2 3/3] arm64: dts: qcom: sdm845: Add SD nodes for sdm845-mtp

[Doug Anderson]

Hi,

On Thu, Dec 6, 2018 at 10:46 AM Evan Green <evgreen@chromium.org> wrote:
>
> Enable support for one of the micro SD slots on the MTP.
>
> Signed-off-by: Evan Green <evgreen@chromium.org>
> ---
>
> Changes in v2:
>  - Fixed alphabetization of node placement in sdm845-mtp.dtsi (Doug)
>  - Fixed card detect name to match schematics (Doug).
>  - Moved comment about drive strength next to the drive-strength entry
>  (Doug)
>  - Removed drive-strength from card detect input pin (Doug).
>  - Consolidated tlmm nodes in MTP.
>
>  arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 58 ++++++++++++++++++++++++-
>  1 file changed, 56 insertions(+), 2 deletions(-)

Reviewed-by: Douglas Anderson <dianders@chromium.org>

Re: [PATCH v2 2/3] arm64: dts: qcom: sdm845: Add SD node

[Bjorn Andersson]

On Thu 06 Dec 10:45 PST 2018, Evan Green wrote:

> Add one of the two SD controllers to SDM845.
> 
> Signed-off-by: Evan Green <evgreen@chromium.org>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> ---
> 
> Changes in v2:
>  - Reworded commit message to note that there are multiple SD
>  controllers.
> 
>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 1419b0098cb38..bb8eacdf40910 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1078,6 +1078,21 @@
>  			};
>  		};
>  
> +		sdhc_2: sdhci@8804000 {
> +			compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
> +			reg = <0x8804000 0x1000>;
> +
> +			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "hc_irq", "pwr_irq";
> +
> +			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> +				 <&gcc GCC_SDCC2_APPS_CLK>;
> +			clock-names = "iface", "core";
> +
> +			status = "disabled";
> +		};
> +
>  		usb_1_hsphy: phy@88e2000 {
>  			compatible = "qcom,sdm845-qusb2-phy";
>  			reg = <0x88e2000 0x400>;
> -- 
> 2.18.1
> 

Re: [PATCH v2 3/3] arm64: dts: qcom: sdm845: Add SD nodes for sdm845-mtp

[Bjorn Andersson]

On Thu 06 Dec 10:45 PST 2018, Evan Green wrote:

> Enable support for one of the micro SD slots on the MTP.
> 
> Signed-off-by: Evan Green <evgreen@chromium.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> ---
> 
> Changes in v2:
>  - Fixed alphabetization of node placement in sdm845-mtp.dtsi (Doug)
>  - Fixed card detect name to match schematics (Doug).
>  - Moved comment about drive strength next to the drive-strength entry
>  (Doug)
>  - Removed drive-strength from card detect input pin (Doug).
>  - Consolidated tlmm nodes in MTP.
> 
>  arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 58 ++++++++++++++++++++++++-
>  1 file changed, 56 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
> index b3def03581775..cde76da42cbb7 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
> @@ -7,6 +7,7 @@
>  
>  /dts-v1/;
>  
> +#include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>  #include "sdm845.dtsi"
>  
> @@ -358,8 +359,16 @@
>  	status = "okay";
>  };
>  
> -&tlmm {
> -	gpio-reserved-ranges = <0 4>, <81 4>;
> +&sdhc_2 {
> +	status = "okay";
> +
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>;
> +
> +	vmmc-supply = <&vreg_l21a_2p95>;
> +	vqmmc-supply = <&vddpx_2>;
> +
> +	cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
>  };
>  
>  &uart9 {
> @@ -450,3 +459,48 @@
>  		bias-pull-up;
>  	};
>  };
> +
> +&tlmm {
> +	gpio-reserved-ranges = <0 4>, <81 4>;
> +
> +	sdc2_clk: sdc2-clk {
> +		pinconf {
> +			pins = "sdc2_clk";
> +			bias-disable;
> +
> +			/*
> +			 * It seems that mmc_test reports errors if drive
> +			 * strength is not 16 on clk, cmd, and data pins.
> +			 */
> +			drive-strength = <16>;
> +		};
> +	};
> +
> +	sdc2_cmd: sdc2-cmd {
> +		pinconf {
> +			pins = "sdc2_cmd";
> +			bias-pull-up;
> +			drive-strength = <16>;
> +		};
> +	};
> +
> +	sdc2_data: sdc2-data {
> +		pinconf {
> +			pins = "sdc2_data";
> +			bias-pull-up;
> +			drive-strength = <16>;
> +		};
> +	};
> +
> +	sd_card_det_n: sd-card-det-n {
> +		pinmux {
> +			pins = "gpio126";
> +			function = "gpio";
> +		};
> +
> +		pinconf {
> +			pins = "gpio126";
> +			bias-pull-up;
> +		};
> +	};
> +};
> -- 
> 2.18.1
>