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received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: RKgA57IYgwXPnV2RqP1lWhbpGibzl6QjTuOjeSdq9eA09TikYO4BwnQyIWiDh4aa3hshKmKh1JDnQQev7SRWJis0HCupQn7l03xU4GA/3KhdWT1+AFxeASm+dq6inR3WAJWkPB1tko4qu4xfb6eKTru3T7tpTqQ9s83aryR4z/SKJji6ykmZbXxF5DujMEXvPaNw9Ibf9euC2FmPDdCmHj9ekHk4MWnscWHdSJgn0aeHZG1xobsJ7oUzrAmhLpD+4SB+FgwHbQVvdC8c6bUfSCtAQKy5d9bMBDpf5UKAta7+kDKdoxF++IQKwPC1VlW6 spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: be674ff2-28dd-4b78-72f4-08d6609d071b X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Dec 2018 01:48:06.7375 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1742 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marek, On Thu, Dec 13, 2018 at 01:55:29AM +0100, Marek Vasut wrote: > On 12/13/2018 01:41 AM, Paul Burton wrote: > > This patch has broken the UART on my Ingenic JZ4780 based MIPS Creator > > Ci20 board. After this patch the system seems to detect garbage input > > that is recognized as SysRq triggers which spam the console & eventuall= y > > reset the system. > >=20 > > One thing of note is that both serial8250_do_startup() & > > serial8250_do_shutdown() contain comments that explicitly state their > > expectation that the FIFOs will be disabled by serial8250_clear_fifos()= , > > which is no longer true after this patch. > >=20 > > I found that restoring the old behaviour for serial8250_do_startup() is > > enough to make my system work again, but this is obviously a hack: >% > > Any ideas? Given the mismatch between this patch & comments that clearl= y > > expect the old behaviour I think the __do_stop_tx_rs485() case probably > > needs something different to other callers. >=20 > The problem the original patch fixed was that too many bits were cleared > in the FCR on OMAP3/AM335x . If you have such a system (a beaglebone or > similar), you can come up with a solution which can accommodate both the > JZ4780 and AM335x. Can you take a look ? The datasheet for both should > be public too. I don't have such a system, but hey - the Ingenic JZ4780 manual is public too [1] so you have just as much opportunity to fix it :) I wonder whether the issue may be the JZ4780 UART not automatically resetting the FIFOs when FCR[0] changes. This is a guess, but the manual doesn't explicitly say it'll happen & the programming example it gives says to explicitly clear the FIFOs using FCR[2:1]. Since this is what the kernel has been doing for at least the whole git era I wouldn't be surprised if other devices are bitten by the change as people start trying 4.20 on them. So I think the safest option might be to restore the original behaviour & just keep your change for the __do_stop_tx_rs485() path specifically, something like the below. Could you test it on your system? Assuming it works I'll clean it up & submit. Otherwise your patch is a regression so I think a revert would make sense until the problem is found. Thanks, Paul [1] ftp://ftp.ingenic.cn/SOC/JZ4780/JZ4780_pm.pdf --- diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/= 8250_port.c index f776b3eafb96..0df0ed437a87 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -550,7 +550,7 @@ static unsigned int serial_icr_read(struct uart_8250_po= rt *up, int offset) /* * FIFO support. */ -static void serial8250_clear_fifos(struct uart_8250_port *p) +static void __serial8250_clear_fifos(struct uart_8250_port *p, int clr) { unsigned char fcr; unsigned char clr_mask =3D UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT; @@ -558,25 +558,26 @@ static void serial8250_clear_fifos(struct uart_8250_p= ort *p) if (p->capabilities & UART_CAP_FIFO) { /* * Make sure to avoid changing FCR[7:3] and ENABLE_FIFO bits. - * In case ENABLE_FIFO is not set, there is nothing to flush - * so just return. Furthermore, on certain implementations of - * the 8250 core, the FCR[7:3] bits may only be changed under - * specific conditions and changing them if those conditions - * are not met can have nasty side effects. One such core is - * the 8250-omap present in TI AM335x. + * On certain implementations of the 8250 core, the FCR[7:3] + * bits may only be changed under specific conditions and + * changing them if those conditions are not met can have nasty + * side effects. One such core is the 8250-omap present in TI + * AM335x. */ fcr =3D serial_in(p, UART_FCR); + serial_out(p, UART_FCR, fcr | clr_mask); + serial_out(p, UART_FCR, fcr & ~clr); + } +} =20 - /* FIFO is not enabled, there's nothing to clear. */ - if (!(fcr & UART_FCR_ENABLE_FIFO)) - return; - - fcr |=3D clr_mask; - serial_out(p, UART_FCR, fcr); +static void serial8250_clear_fifos(struct uart_8250_port *p) +{ + __serial8250_clear_fifos(p, 0); +} =20 - fcr &=3D ~clr_mask; - serial_out(p, UART_FCR, fcr); - } +static void serial8250_clear_and_disable_fifos(struct uart_8250_port *p) +{ + __serial8250_clear_fifos(p, UART_FCR_ENABLE_FIFO); } =20 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *= p) @@ -595,7 +596,7 @@ static enum hrtimer_restart serial8250_em485_handle_sto= p_tx(struct hrtimer *t); =20 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p) { - serial8250_clear_fifos(p); + serial8250_clear_and_disable_fifos(p); serial_out(p, UART_FCR, p->fcr); } EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos); @@ -1364,7 +1365,7 @@ static void autoconfig(struct uart_8250_port *up) serial_out(up, UART_RSA_FRR, 0); #endif serial8250_out_MCR(up, save_mcr); - serial8250_clear_fifos(up); + serial8250_clear_and_disable_fifos(up); serial_in(up, UART_RX); if (up->capabilities & UART_CAP_UUE) serial_out(up, UART_IER, UART_IER_UUE); @@ -2210,7 +2211,7 @@ int serial8250_do_startup(struct uart_port *port) * Clear the FIFO buffers and disable them. * (they will be reenabled in set_termios()) */ - serial8250_clear_fifos(up); + serial8250_clear_and_disable_fifos(up); =20 /* * Clear the interrupt registers. @@ -2460,7 +2461,7 @@ void serial8250_do_shutdown(struct uart_port *port) */ serial_port_out(port, UART_LCR, serial_port_in(port, UART_LCR) & ~UART_LCR_SBC); - serial8250_clear_fifos(up); + serial8250_clear_and_disable_fifos(up); =20 #ifdef CONFIG_SERIAL_8250_RSA /*