From: Xiaowei Bao <xiaowei.bao@nxp.com>
To: bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com,
shawnguo@kernel.org, leoyang.li@nxp.com, kishon@ti.com,
lorenzo.pieralisi@arm.com, arnd@arndb.de,
gregkh@linuxfoundation.org, minghuan.Lian@nxp.com,
mingkai.hu@nxp.com, roy.zang@nxp.com,
kstewart@linuxfoundation.org, cyrille.pitchen@free-electrons.com,
pombredanne@nexb.com, shawn.lin@rock-chips.com,
niklas.cassel@axis.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linuxppc-dev@lists.ozlabs.org
Cc: Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: [PATCHv4 2/4] arm64: dts: Add the PCIE EP node in dts
Date: Tue, 8 Jan 2019 11:09:20 +0800 [thread overview]
Message-ID: <20190108030922.24031-2-xiaowei.bao@nxp.com> (raw)
In-Reply-To: <20190108030922.24031-1-xiaowei.bao@nxp.com>
Add the PCIE EP node in dts for ls1046a.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
v2:
- Add the SoC specific compatibles.
v3:
- no change
v4:
- no change
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 34 +++++++++++++++++++++++-
1 files changed, 33 insertions(+), 1 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 9a2106e..e373826 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -657,6 +657,17 @@
status = "disabled";
};
+ pcie_ep@3400000 {
+ compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x40 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
+ num-lanes = <2>;
+ status = "disabled";
+ };
+
pcie@3500000 {
compatible = "fsl,ls1046a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
@@ -683,6 +694,17 @@
status = "disabled";
};
+ pcie_ep@3500000 {
+ compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x48 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
+ num-lanes = <2>;
+ status = "disabled";
+ };
+
pcie@3600000 {
compatible = "fsl,ls1046a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
@@ -709,6 +731,17 @@
status = "disabled";
};
+ pcie_ep@3600000 {
+ compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x00100000
+ 0x50 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
+ num-lanes = <2>;
+ status = "disabled";
+ };
+
qdma: dma-controller@8380000 {
compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
@@ -729,7 +762,6 @@
queue-sizes = <64 64>;
big-endian;
};
-
};
reserved-memory {
--
1.7.1
next prev parent reply other threads:[~2019-01-08 3:15 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-08 3:09 [PATCHv4 1/4] dt-bindings: add DT binding for the layerscape PCIe controller with EP mode Xiaowei Bao
2019-01-08 3:09 ` Xiaowei Bao [this message]
2019-01-08 3:09 ` [PATCHv4 3/4] pci: layerscape: Add the EP mode support Xiaowei Bao
2019-01-08 3:09 ` [PATCHv4 4/4] misc: pci_endpoint_test: Add the layerscape EP device support Xiaowei Bao
2019-01-11 14:31 ` [PATCHv4 1/4] dt-bindings: add DT binding for the layerscape PCIe controller with EP mode Rob Herring
2019-01-16 3:50 ` Xiaowei Bao
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