* [PATCH 0/3] Add coresight support for SDM845
@ 2019-01-09 17:46 Sai Prakash Ranjan
2019-01-09 17:46 ` [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support Sai Prakash Ranjan
` (2 more replies)
0 siblings, 3 replies; 16+ messages in thread
From: Sai Prakash Ranjan @ 2019-01-09 17:46 UTC (permalink / raw)
To: Rob Herring, Mathieu Poirier, Suzuki K Poulose, Leo Yan,
Alexander Shishkin, Andy Gross, David Brown, devicetree,
Mark Rutland
Cc: Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel,
linux-kernel, linux-arm-msm, Sai Prakash Ranjan
This patch series adds support for coresight on SDM845.
* Patch 1 adds device tree nodes for SDM845 coresight components.
* Patch 2 enables support for ETMv4.2 and enables SDM845 to make
use of same driver(etm4x).
* Patch 3 is a trivial removal of duplicate header file.
Patch 1 and 2 depends on below AOSS QMP patches by Bjorn:
https://patchwork.kernel.org/patch/10749469/
https://patchwork.kernel.org/patch/10749481/
https://patchwork.kernel.org/patch/10749479/
https://patchwork.kernel.org/patch/10749475/
This patch series has been tested on SDM845 MTP.
Sai Prakash Ranjan (3):
arm64: dts: qcom: sdm845: Add Coresight support
coresight: etm4x: Add support to enable ETMv4.2
arm64: dts: qcom: sdm845: Remove the duplicate header inclusion
.../arm64/boot/dts/qcom/sdm845-coresight.dtsi | 437 ++++++++++++++++++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 +-
drivers/hwtracing/coresight/coresight-etm4x.c | 2 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
4 files changed, 441 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support 2019-01-09 17:46 [PATCH 0/3] Add coresight support for SDM845 Sai Prakash Ranjan @ 2019-01-09 17:46 ` Sai Prakash Ranjan 2019-01-11 18:46 ` Mathieu Poirier 2019-01-13 7:23 ` Bjorn Andersson 2019-01-09 17:46 ` [PATCH 2/3] coresight: etm4x: Add support to enable ETMv4.2 Sai Prakash Ranjan 2019-01-09 17:46 ` [PATCH 3/3] arm64: dts: qcom: sdm845: Remove the duplicate header inclusion Sai Prakash Ranjan 2 siblings, 2 replies; 16+ messages in thread From: Sai Prakash Ranjan @ 2019-01-09 17:46 UTC (permalink / raw) To: Rob Herring, Mathieu Poirier, Suzuki K Poulose, Leo Yan, Alexander Shishkin, Andy Gross, David Brown, devicetree, Mark Rutland Cc: Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel, linux-kernel, linux-arm-msm, Sai Prakash Ranjan Add coresight components found on Qualcomm SDM845 SoC. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> --- .../arm64/boot/dts/qcom/sdm845-coresight.dtsi | 437 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 + 2 files changed, 439 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi diff --git a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi new file mode 100644 index 000000000000..b6ef250b9186 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 Coresight DTS + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +&soc { + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x06002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x06041000 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6043000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x06043000 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + funnel2_out: endpoint { + remote-endpoint = + <&merge_funnel_in2>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + funnel2_in5: endpoint { + remote-endpoint = + <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x06045000 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@2 { + reg = <2>; + merge_funnel_in2: endpoint { + remote-endpoint = + <&funnel2_out>; + }; + }; + }; + }; + + replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x06046000 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@6047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x06047000 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + etf_in: endpoint { + remote-endpoint = <&merge_funnel_out>; + }; + }; + }; + }; + + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x06048000 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = <&replicator_out>; + }; + }; + }; + }; + + etm@7040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x07040000 0x1000>; + + cpu = <&CPU0>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x07140000 0x1000>; + + cpu = <&CPU1>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x07240000 0x1000>; + + cpu = <&CPU2>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x07340000 0x1000>; + + cpu = <&CPU3>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&apss_funnel_in3>; + }; + }; + }; + }; + + etm@7440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x07440000 0x1000>; + + cpu = <&CPU4>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = <&apss_funnel_in4>; + }; + }; + }; + }; + + etm@7540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x07540000 0x1000>; + + cpu = <&CPU5>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = <&apss_funnel_in5>; + }; + }; + }; + }; + + etm@7640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x07640000 0x1000>; + + cpu = <&CPU6>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = <&apss_funnel_in6>; + }; + }; + }; + }; + + etm@7740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x07740000 0x1000>; + + cpu = <&CPU7>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = <&apss_funnel_in7>; + }; + }; + }; + }; + + funnel@7800000 { /* APSS Funnel */ + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x07800000 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = + <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = + <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = + <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = + <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = + <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = + <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = + <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = + <&etm7_out>; + }; + }; + }; + }; + + funnel@7810000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x07810000 0x1000>; + + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = + <&funnel2_in5>; + }; + }; + }; + + in-ports { + port { + apss_merge_funnel_in: endpoint { + remote-endpoint = + <&apss_funnel_out>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index c27cbd3bcb0a..03683179b8f7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1853,3 +1853,5 @@ }; }; }; + +#include "sdm845-coresight.dtsi" -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support 2019-01-09 17:46 ` [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support Sai Prakash Ranjan @ 2019-01-11 18:46 ` Mathieu Poirier 2019-01-12 12:51 ` saiprakash.ranjan 2019-01-13 7:23 ` Bjorn Andersson 1 sibling, 1 reply; 16+ messages in thread From: Mathieu Poirier @ 2019-01-11 18:46 UTC (permalink / raw) To: Sai Prakash Ranjan Cc: Rob Herring, Suzuki K Poulose, Leo Yan, Alexander Shishkin, Andy Gross, David Brown, devicetree, Mark Rutland, Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel, linux-kernel, linux-arm-msm Hi Sai, On Wed, Jan 09, 2019 at 11:16:47PM +0530, Sai Prakash Ranjan wrote: > Add coresight components found on Qualcomm SDM845 SoC. > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > --- > .../arm64/boot/dts/qcom/sdm845-coresight.dtsi | 437 ++++++++++++++++++ > arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 + > 2 files changed, 439 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi > new file mode 100644 > index 000000000000..b6ef250b9186 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi > @@ -0,0 +1,437 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * SDM845 Coresight DTS > + * > + * Copyright (c) 2019, The Linux Foundation. All rights reserved. > + */ > + > +&soc { > + stm@6002000 { > + compatible = "arm,coresight-stm", "arm,primecell"; > + reg = <0x06002000 0x1000>, > + <0x16280000 0x180000>; > + reg-names = "stm-base", "stm-stimulus-base"; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + stm_out: endpoint { > + remote-endpoint = <&funnel0_in7>; > + }; > + }; > + }; > + }; > + > + funnel@6041000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x06041000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + funnel0_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in0>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@7 { > + reg = <7>; > + funnel0_in7: endpoint { > + remote-endpoint = <&stm_out>; > + }; > + }; > + }; > + }; > + > + funnel@6043000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x06043000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + funnel2_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in2>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@5 { > + reg = <5>; > + funnel2_in5: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_out>; > + }; > + }; > + }; > + }; > + > + funnel@6045000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x06045000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + merge_funnel_out: endpoint { > + remote-endpoint = <&etf_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + merge_funnel_in0: endpoint { > + remote-endpoint = > + <&funnel0_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + merge_funnel_in2: endpoint { > + remote-endpoint = > + <&funnel2_out>; > + }; > + }; > + }; > + }; > + > + replicator@6046000 { > + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; > + reg = <0x06046000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + replicator_out: endpoint { > + remote-endpoint = <&etr_in>; > + }; > + }; > + }; > + > + in-ports { > + port { > + replicator_in: endpoint { > + remote-endpoint = <&etf_out>; > + }; > + }; > + }; > + }; > + > + etf@6047000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0x06047000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etf_out: endpoint { > + remote-endpoint = <&replicator_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <1>; > + etf_in: endpoint { > + remote-endpoint = <&merge_funnel_out>; > + }; > + }; > + }; > + }; > + > + etr@6048000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0x06048000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + in-ports { > + port { > + etr_in: endpoint { > + remote-endpoint = <&replicator_out>; > + }; > + }; > + }; > + }; > + > + etm@7040000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; I'm a little curious as to why you need to bypass the normal AMBA bus discovery method by forcing the peripheral ID. Tracers don't show up the way other coresight devices do at boot time? > + reg = <0x07040000 0x1000>; > + > + cpu = <&CPU0>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm0_out: endpoint { > + remote-endpoint = <&apss_funnel_in0>; > + }; > + }; > + }; > + }; > + > + etm@7140000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07140000 0x1000>; > + > + cpu = <&CPU1>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm1_out: endpoint { > + remote-endpoint = <&apss_funnel_in1>; > + }; > + }; > + }; > + }; > + > + etm@7240000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07240000 0x1000>; > + > + cpu = <&CPU2>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm2_out: endpoint { > + remote-endpoint = <&apss_funnel_in2>; > + }; > + }; > + }; > + }; > + > + etm@7340000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07340000 0x1000>; > + > + cpu = <&CPU3>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm3_out: endpoint { > + remote-endpoint = <&apss_funnel_in3>; > + }; > + }; > + }; > + }; > + > + etm@7440000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07440000 0x1000>; > + > + cpu = <&CPU4>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm4_out: endpoint { > + remote-endpoint = <&apss_funnel_in4>; > + }; > + }; > + }; > + }; > + > + etm@7540000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07540000 0x1000>; > + > + cpu = <&CPU5>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm5_out: endpoint { > + remote-endpoint = <&apss_funnel_in5>; > + }; > + }; > + }; > + }; > + > + etm@7640000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07640000 0x1000>; > + > + cpu = <&CPU6>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm6_out: endpoint { > + remote-endpoint = <&apss_funnel_in6>; > + }; > + }; > + }; > + }; > + > + etm@7740000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07740000 0x1000>; > + > + cpu = <&CPU7>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm7_out: endpoint { > + remote-endpoint = <&apss_funnel_in7>; > + }; > + }; > + }; > + }; > + > + funnel@7800000 { /* APSS Funnel */ > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x07800000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + apss_funnel_out: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + apss_funnel_in0: endpoint { > + remote-endpoint = > + <&etm0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + apss_funnel_in1: endpoint { > + remote-endpoint = > + <&etm1_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + apss_funnel_in2: endpoint { > + remote-endpoint = > + <&etm2_out>; > + }; > + }; > + > + port@3 { > + reg = <3>; > + apss_funnel_in3: endpoint { > + remote-endpoint = > + <&etm3_out>; > + }; > + }; > + > + port@4 { > + reg = <4>; > + apss_funnel_in4: endpoint { > + remote-endpoint = > + <&etm4_out>; > + }; > + }; > + > + port@5 { > + reg = <5>; > + apss_funnel_in5: endpoint { > + remote-endpoint = > + <&etm5_out>; > + }; > + }; > + > + port@6 { > + reg = <6>; > + apss_funnel_in6: endpoint { > + remote-endpoint = > + <&etm6_out>; > + }; > + }; > + > + port@7 { > + reg = <7>; > + apss_funnel_in7: endpoint { > + remote-endpoint = > + <&etm7_out>; > + }; > + }; > + }; > + }; > + > + funnel@7810000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x07810000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + apss_merge_funnel_out: endpoint { > + remote-endpoint = > + <&funnel2_in5>; > + }; > + }; > + }; > + > + in-ports { > + port { > + apss_merge_funnel_in: endpoint { > + remote-endpoint = > + <&apss_funnel_out>; > + }; > + }; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index c27cbd3bcb0a..03683179b8f7 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -1853,3 +1853,5 @@ > }; > }; > }; > + > +#include "sdm845-coresight.dtsi" > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support 2019-01-11 18:46 ` Mathieu Poirier @ 2019-01-12 12:51 ` saiprakash.ranjan 2019-01-14 15:35 ` Mathieu Poirier 0 siblings, 1 reply; 16+ messages in thread From: saiprakash.ranjan @ 2019-01-12 12:51 UTC (permalink / raw) To: Mathieu Poirier Cc: Rob Herring, Suzuki K Poulose, Leo Yan, Alexander Shishkin, Andy Gross, David Brown, devicetree, Mark Rutland, Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel, linux-kernel, linux-arm-msm, linux-arm-msm-owner Hi Mathieu, >> + >> + etm@7040000 { >> + compatible = "arm,coresight-etm4x", "arm,primecell"; >> + arm,primecell-periphid = <0x000bb95d>; > > I'm a little curious as to why you need to bypass the normal AMBA bus > discovery > method by forcing the peripheral ID. Tracers don't show up the way > other > coresight devices do at boot time? > Yes on some Qcom SoC's like SDM845 and also on some previous ones, for ETM(only) amba bus discovery method fails because of wrong pid read from the registers. So we have to force this primecell peripheral ids to probe etm. - Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support 2019-01-12 12:51 ` saiprakash.ranjan @ 2019-01-14 15:35 ` Mathieu Poirier 2019-01-15 16:29 ` Sai Prakash Ranjan 0 siblings, 1 reply; 16+ messages in thread From: Mathieu Poirier @ 2019-01-14 15:35 UTC (permalink / raw) To: saiprakash.ranjan Cc: Rob Herring, Suzuki K Poulose, Leo Yan, Alexander Shishkin, Andy Gross, David Brown, devicetree, Mark Rutland, Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel, linux-kernel, linux-arm-msm, linux-arm-msm-owner On Sat, Jan 12, 2019 at 06:21:00PM +0530, saiprakash.ranjan@codeaurora.org wrote: > Hi Mathieu, > > > > + > > > + etm@7040000 { > > > + compatible = "arm,coresight-etm4x", "arm,primecell"; > > > + arm,primecell-periphid = <0x000bb95d>; > > > > I'm a little curious as to why you need to bypass the normal AMBA bus > > discovery > > method by forcing the peripheral ID. Tracers don't show up the way > > other > > coresight devices do at boot time? > > > > Yes on some Qcom SoC's like SDM845 and also on some previous ones, for > ETM(only) amba bus discovery method fails because of wrong pid read from the > registers. So we have to force this primecell peripheral ids to probe etm. Ok, if that is the case please add a comment to explain the situation. Otherwise someone will assuredly ask again in the future. Mathieu > > - Sai > > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of > Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support 2019-01-14 15:35 ` Mathieu Poirier @ 2019-01-15 16:29 ` Sai Prakash Ranjan 0 siblings, 0 replies; 16+ messages in thread From: Sai Prakash Ranjan @ 2019-01-15 16:29 UTC (permalink / raw) To: Mathieu Poirier Cc: Mark Rutland, devicetree, Rajendra Nayak, Suzuki K Poulose, Alexander Shishkin, linux-arm-msm, linux-kernel, David Brown, Rob Herring, Sibi Sankar, Vivek Gautam, Leo Yan, Andy Gross, linux-arm-msm-owner, linux-arm-kernel Hi Mathieu, On 1/14/2019 9:05 PM, Mathieu Poirier wrote: > On Sat, Jan 12, 2019 at 06:21:00PM +0530, saiprakash.ranjan@codeaurora.org wrote: >> Hi Mathieu, >> >>>> + >>>> + etm@7040000 { >>>> + compatible = "arm,coresight-etm4x", "arm,primecell"; >>>> + arm,primecell-periphid = <0x000bb95d>; >>> >>> I'm a little curious as to why you need to bypass the normal AMBA bus >>> discovery >>> method by forcing the peripheral ID. Tracers don't show up the way >>> other >>> coresight devices do at boot time? >>> >> >> Yes on some Qcom SoC's like SDM845 and also on some previous ones, for >> ETM(only) amba bus discovery method fails because of wrong pid read from the >> registers. So we have to force this primecell peripheral ids to probe etm. > > Ok, if that is the case please add a comment to explain the situation. > Otherwise someone will assuredly ask again in the future. > Sure, will add it in the next version. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support 2019-01-09 17:46 ` [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support Sai Prakash Ranjan 2019-01-11 18:46 ` Mathieu Poirier @ 2019-01-13 7:23 ` Bjorn Andersson 2019-01-15 16:27 ` Sai Prakash Ranjan 1 sibling, 1 reply; 16+ messages in thread From: Bjorn Andersson @ 2019-01-13 7:23 UTC (permalink / raw) To: Sai Prakash Ranjan Cc: Rob Herring, Mathieu Poirier, Suzuki K Poulose, Leo Yan, Alexander Shishkin, Andy Gross, David Brown, devicetree, Mark Rutland, Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel, linux-kernel, linux-arm-msm On Wed 09 Jan 09:46 PST 2019, Sai Prakash Ranjan wrote: > Add coresight components found on Qualcomm SDM845 SoC. > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Hi Sai, The content of this patch looks good, but please fold it into sdm845.dtsi (keep the nodes sorted by address). And mention below the --- that this depends on my AMBA bus pclk change and include the URL: https://lore.kernel.org/lkml/20190106080915.4493-7-bjorn.andersson@linaro.org/ Regards, Bjorn > --- > .../arm64/boot/dts/qcom/sdm845-coresight.dtsi | 437 ++++++++++++++++++ > arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 + > 2 files changed, 439 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi > new file mode 100644 > index 000000000000..b6ef250b9186 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi > @@ -0,0 +1,437 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * SDM845 Coresight DTS > + * > + * Copyright (c) 2019, The Linux Foundation. All rights reserved. > + */ > + > +&soc { > + stm@6002000 { > + compatible = "arm,coresight-stm", "arm,primecell"; > + reg = <0x06002000 0x1000>, > + <0x16280000 0x180000>; > + reg-names = "stm-base", "stm-stimulus-base"; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + stm_out: endpoint { > + remote-endpoint = <&funnel0_in7>; > + }; > + }; > + }; > + }; > + > + funnel@6041000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x06041000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + funnel0_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in0>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@7 { > + reg = <7>; > + funnel0_in7: endpoint { > + remote-endpoint = <&stm_out>; > + }; > + }; > + }; > + }; > + > + funnel@6043000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x06043000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + funnel2_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in2>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@5 { > + reg = <5>; > + funnel2_in5: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_out>; > + }; > + }; > + }; > + }; > + > + funnel@6045000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x06045000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + merge_funnel_out: endpoint { > + remote-endpoint = <&etf_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + merge_funnel_in0: endpoint { > + remote-endpoint = > + <&funnel0_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + merge_funnel_in2: endpoint { > + remote-endpoint = > + <&funnel2_out>; > + }; > + }; > + }; > + }; > + > + replicator@6046000 { > + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; > + reg = <0x06046000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + replicator_out: endpoint { > + remote-endpoint = <&etr_in>; > + }; > + }; > + }; > + > + in-ports { > + port { > + replicator_in: endpoint { > + remote-endpoint = <&etf_out>; > + }; > + }; > + }; > + }; > + > + etf@6047000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0x06047000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etf_out: endpoint { > + remote-endpoint = <&replicator_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <1>; > + etf_in: endpoint { > + remote-endpoint = <&merge_funnel_out>; > + }; > + }; > + }; > + }; > + > + etr@6048000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0x06048000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + in-ports { > + port { > + etr_in: endpoint { > + remote-endpoint = <&replicator_out>; > + }; > + }; > + }; > + }; > + > + etm@7040000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07040000 0x1000>; > + > + cpu = <&CPU0>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm0_out: endpoint { > + remote-endpoint = <&apss_funnel_in0>; > + }; > + }; > + }; > + }; > + > + etm@7140000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07140000 0x1000>; > + > + cpu = <&CPU1>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm1_out: endpoint { > + remote-endpoint = <&apss_funnel_in1>; > + }; > + }; > + }; > + }; > + > + etm@7240000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07240000 0x1000>; > + > + cpu = <&CPU2>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm2_out: endpoint { > + remote-endpoint = <&apss_funnel_in2>; > + }; > + }; > + }; > + }; > + > + etm@7340000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07340000 0x1000>; > + > + cpu = <&CPU3>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm3_out: endpoint { > + remote-endpoint = <&apss_funnel_in3>; > + }; > + }; > + }; > + }; > + > + etm@7440000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07440000 0x1000>; > + > + cpu = <&CPU4>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm4_out: endpoint { > + remote-endpoint = <&apss_funnel_in4>; > + }; > + }; > + }; > + }; > + > + etm@7540000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07540000 0x1000>; > + > + cpu = <&CPU5>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm5_out: endpoint { > + remote-endpoint = <&apss_funnel_in5>; > + }; > + }; > + }; > + }; > + > + etm@7640000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07640000 0x1000>; > + > + cpu = <&CPU6>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm6_out: endpoint { > + remote-endpoint = <&apss_funnel_in6>; > + }; > + }; > + }; > + }; > + > + etm@7740000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + arm,primecell-periphid = <0x000bb95d>; > + reg = <0x07740000 0x1000>; > + > + cpu = <&CPU7>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + etm7_out: endpoint { > + remote-endpoint = <&apss_funnel_in7>; > + }; > + }; > + }; > + }; > + > + funnel@7800000 { /* APSS Funnel */ > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x07800000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + apss_funnel_out: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + apss_funnel_in0: endpoint { > + remote-endpoint = > + <&etm0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + apss_funnel_in1: endpoint { > + remote-endpoint = > + <&etm1_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + apss_funnel_in2: endpoint { > + remote-endpoint = > + <&etm2_out>; > + }; > + }; > + > + port@3 { > + reg = <3>; > + apss_funnel_in3: endpoint { > + remote-endpoint = > + <&etm3_out>; > + }; > + }; > + > + port@4 { > + reg = <4>; > + apss_funnel_in4: endpoint { > + remote-endpoint = > + <&etm4_out>; > + }; > + }; > + > + port@5 { > + reg = <5>; > + apss_funnel_in5: endpoint { > + remote-endpoint = > + <&etm5_out>; > + }; > + }; > + > + port@6 { > + reg = <6>; > + apss_funnel_in6: endpoint { > + remote-endpoint = > + <&etm6_out>; > + }; > + }; > + > + port@7 { > + reg = <7>; > + apss_funnel_in7: endpoint { > + remote-endpoint = > + <&etm7_out>; > + }; > + }; > + }; > + }; > + > + funnel@7810000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x07810000 0x1000>; > + > + power-domains = <&aoss_qmp AOSS_QMP_QDSS_CLK>; > + > + out-ports { > + port { > + apss_merge_funnel_out: endpoint { > + remote-endpoint = > + <&funnel2_in5>; > + }; > + }; > + }; > + > + in-ports { > + port { > + apss_merge_funnel_in: endpoint { > + remote-endpoint = > + <&apss_funnel_out>; > + }; > + }; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index c27cbd3bcb0a..03683179b8f7 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -1853,3 +1853,5 @@ > }; > }; > }; > + > +#include "sdm845-coresight.dtsi" > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support 2019-01-13 7:23 ` Bjorn Andersson @ 2019-01-15 16:27 ` Sai Prakash Ranjan 2019-01-17 19:50 ` Bjorn Andersson 0 siblings, 1 reply; 16+ messages in thread From: Sai Prakash Ranjan @ 2019-01-15 16:27 UTC (permalink / raw) To: Bjorn Andersson Cc: Rob Herring, Mathieu Poirier, Suzuki K Poulose, Leo Yan, Alexander Shishkin, Andy Gross, David Brown, devicetree, Mark Rutland, Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel, linux-kernel, linux-arm-msm Hi Bjorn, Thanks for the review. Please find my comments inline. On 1/13/2019 12:53 PM, Bjorn Andersson wrote: > On Wed 09 Jan 09:46 PST 2019, Sai Prakash Ranjan wrote: > >> Add coresight components found on Qualcomm SDM845 SoC. >> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > > Hi Sai, > > The content of this patch looks good, but please fold it into > sdm845.dtsi (keep the nodes sorted by address). > I had looked at the sample from hi6220 for coresight and decided to keep sdm845 coresight dtsi in separate file as it would look much cleaner than mixing it with main dtsi file. Also I guess it would make coresight topology more understandable if we keep it separately (plus there are about 400+ lines of coresight dt entries). Is there any reason for wanting coresight entries merged into sdm845.dtsi file? If you still prefer it, I can make the change in the next version. > And mention below the --- that this depends on my AMBA bus pclk change > and include the URL: > > https://lore.kernel.org/lkml/20190106080915.4493-7-bjorn.andersson@linaro.org/ > I had mentioned this dependency in the cover letter. But I suppose I can mention it here as well. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support 2019-01-15 16:27 ` Sai Prakash Ranjan @ 2019-01-17 19:50 ` Bjorn Andersson 2019-01-18 3:00 ` Sai Prakash Ranjan 0 siblings, 1 reply; 16+ messages in thread From: Bjorn Andersson @ 2019-01-17 19:50 UTC (permalink / raw) To: Sai Prakash Ranjan Cc: Rob Herring, Mathieu Poirier, Suzuki K Poulose, Leo Yan, Alexander Shishkin, Andy Gross, David Brown, devicetree, Mark Rutland, Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel, linux-kernel, linux-arm-msm On Tue 15 Jan 08:27 PST 2019, Sai Prakash Ranjan wrote: > Hi Bjorn, > > Thanks for the review. Please find my comments inline. > > On 1/13/2019 12:53 PM, Bjorn Andersson wrote: > > On Wed 09 Jan 09:46 PST 2019, Sai Prakash Ranjan wrote: > > > > > Add coresight components found on Qualcomm SDM845 SoC. > > > > > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > > > > Hi Sai, > > > > The content of this patch looks good, but please fold it into > > sdm845.dtsi (keep the nodes sorted by address). > > > > I had looked at the sample from hi6220 for coresight and > decided to keep sdm845 coresight dtsi in separate file as it > would look much cleaner than mixing it with main dtsi file. > Also I guess it would make coresight topology more understandable > if we keep it separately (plus there are about 400+ lines of coresight > dt entries). Is there any reason for wanting coresight entries merged > into sdm845.dtsi file? If you still prefer it, I can make the > change in the next version. > There seems to be some variations of this, but we try to keep everything sorted in sdm845.dtsi to avoid having to jump around between the various files. So please merge it into sdm845.dtsi (sorted by address). Regards, Bjorn > > And mention below the --- that this depends on my AMBA bus pclk change > > and include the URL: > > > > https://lore.kernel.org/lkml/20190106080915.4493-7-bjorn.andersson@linaro.org/ > > > > I had mentioned this dependency in the cover letter. But I suppose > I can mention it here as well. > > Thanks, > Sai > > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support 2019-01-17 19:50 ` Bjorn Andersson @ 2019-01-18 3:00 ` Sai Prakash Ranjan 0 siblings, 0 replies; 16+ messages in thread From: Sai Prakash Ranjan @ 2019-01-18 3:00 UTC (permalink / raw) To: Bjorn Andersson Cc: Rob Herring, Mathieu Poirier, Suzuki K Poulose, Leo Yan, Alexander Shishkin, Andy Gross, David Brown, devicetree, Mark Rutland, Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel, linux-kernel, linux-arm-msm On 1/18/2019 1:20 AM, Bjorn Andersson wrote: > > There seems to be some variations of this, but we try to keep everything > sorted in sdm845.dtsi to avoid having to jump around between the various > files. So please merge it into sdm845.dtsi (sorted by address). > Sure will do it. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/3] coresight: etm4x: Add support to enable ETMv4.2 2019-01-09 17:46 [PATCH 0/3] Add coresight support for SDM845 Sai Prakash Ranjan 2019-01-09 17:46 ` [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support Sai Prakash Ranjan @ 2019-01-09 17:46 ` Sai Prakash Ranjan 2019-01-11 18:52 ` Mathieu Poirier 2019-01-09 17:46 ` [PATCH 3/3] arm64: dts: qcom: sdm845: Remove the duplicate header inclusion Sai Prakash Ranjan 2 siblings, 1 reply; 16+ messages in thread From: Sai Prakash Ranjan @ 2019-01-09 17:46 UTC (permalink / raw) To: Rob Herring, Mathieu Poirier, Suzuki K Poulose, Leo Yan, Alexander Shishkin, Andy Gross, David Brown, devicetree, Mark Rutland Cc: Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel, linux-kernel, linux-arm-msm, Sai Prakash Ranjan SDM845 has ETMv4.2 and can use the existing etm4x driver. But the current etm driver checks only for ETMv4.0 and errors out for other etm4x versions. This patch adds this missing support to enable SoC's with ETMv4x to use same driver by checking only the ETM architecture major version number. Without this change, we get below error during etm probe: / # dmesg | grep etm [ 6.660093] coresight-etm4x: probe of 7040000.etm failed with error -22 [ 6.666902] coresight-etm4x: probe of 7140000.etm failed with error -22 [ 6.673708] coresight-etm4x: probe of 7240000.etm failed with error -22 [ 6.680511] coresight-etm4x: probe of 7340000.etm failed with error -22 [ 6.687313] coresight-etm4x: probe of 7440000.etm failed with error -22 [ 6.694113] coresight-etm4x: probe of 7540000.etm failed with error -22 [ 6.700914] coresight-etm4x: probe of 7640000.etm failed with error -22 [ 6.707717] coresight-etm4x: probe of 7740000.etm failed with error -22 With this change, etm probe is successful: / # dmesg | grep coresight [ 6.659198] coresight-etm4x 7040000.etm: CPU0: ETM v4.2 initialized [ 6.665848] coresight-etm4x 7140000.etm: CPU1: ETM v4.2 initialized [ 6.672493] coresight-etm4x 7240000.etm: CPU2: ETM v4.2 initialized [ 6.679129] coresight-etm4x 7340000.etm: CPU3: ETM v4.2 initialized [ 6.685770] coresight-etm4x 7440000.etm: CPU4: ETM v4.2 initialized [ 6.692403] coresight-etm4x 7540000.etm: CPU5: ETM v4.2 initialized [ 6.699024] coresight-etm4x 7640000.etm: CPU6: ETM v4.2 initialized [ 6.705646] coresight-etm4x 7740000.etm: CPU7: ETM v4.2 initialized Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> --- drivers/hwtracing/coresight/coresight-etm4x.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 53e2fb6e86f6..40cf17df5023 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1021,7 +1021,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) cpus_read_unlock(); - if (etm4_arch_supported(drvdata->arch) == false) { + if (etm4_arch_supported(drvdata->arch >> 4) == false) { ret = -EINVAL; goto err_arch_supported; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 52786e9d8926..05d4bd330881 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -136,7 +136,7 @@ #define ETM_MAX_RES_SEL 16 #define ETM_MAX_SS_CMP 8 -#define ETM_ARCH_V4 0x40 +#define ETM_ARCH_V4 0x4 #define ETMv4_SYNC_MASK 0x1F #define ETM_CYC_THRESHOLD_MASK 0xFFF #define ETM_CYC_THRESHOLD_DEFAULT 0x100 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 2/3] coresight: etm4x: Add support to enable ETMv4.2 2019-01-09 17:46 ` [PATCH 2/3] coresight: etm4x: Add support to enable ETMv4.2 Sai Prakash Ranjan @ 2019-01-11 18:52 ` Mathieu Poirier 2019-01-12 12:33 ` saiprakash.ranjan 0 siblings, 1 reply; 16+ messages in thread From: Mathieu Poirier @ 2019-01-11 18:52 UTC (permalink / raw) To: Sai Prakash Ranjan Cc: Rob Herring, Suzuki K Poulose, Leo Yan, Alexander Shishkin, Andy Gross, David Brown, devicetree, Mark Rutland, Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel, linux-kernel, linux-arm-msm On Wed, Jan 09, 2019 at 11:16:48PM +0530, Sai Prakash Ranjan wrote: > SDM845 has ETMv4.2 and can use the existing etm4x driver. > But the current etm driver checks only for ETMv4.0 and > errors out for other etm4x versions. This patch adds this > missing support to enable SoC's with ETMv4x to use same > driver by checking only the ETM architecture major version > number. > > Without this change, we get below error during etm probe: > > / # dmesg | grep etm > [ 6.660093] coresight-etm4x: probe of 7040000.etm failed with error -22 > [ 6.666902] coresight-etm4x: probe of 7140000.etm failed with error -22 > [ 6.673708] coresight-etm4x: probe of 7240000.etm failed with error -22 > [ 6.680511] coresight-etm4x: probe of 7340000.etm failed with error -22 > [ 6.687313] coresight-etm4x: probe of 7440000.etm failed with error -22 > [ 6.694113] coresight-etm4x: probe of 7540000.etm failed with error -22 > [ 6.700914] coresight-etm4x: probe of 7640000.etm failed with error -22 > [ 6.707717] coresight-etm4x: probe of 7740000.etm failed with error -22 > > With this change, etm probe is successful: > > / # dmesg | grep coresight > [ 6.659198] coresight-etm4x 7040000.etm: CPU0: ETM v4.2 initialized > [ 6.665848] coresight-etm4x 7140000.etm: CPU1: ETM v4.2 initialized > [ 6.672493] coresight-etm4x 7240000.etm: CPU2: ETM v4.2 initialized > [ 6.679129] coresight-etm4x 7340000.etm: CPU3: ETM v4.2 initialized > [ 6.685770] coresight-etm4x 7440000.etm: CPU4: ETM v4.2 initialized > [ 6.692403] coresight-etm4x 7540000.etm: CPU5: ETM v4.2 initialized > [ 6.699024] coresight-etm4x 7640000.etm: CPU6: ETM v4.2 initialized > [ 6.705646] coresight-etm4x 7740000.etm: CPU7: ETM v4.2 initialized > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > --- > drivers/hwtracing/coresight/coresight-etm4x.c | 2 +- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > index 53e2fb6e86f6..40cf17df5023 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > @@ -1021,7 +1021,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) > > cpus_read_unlock(); > > - if (etm4_arch_supported(drvdata->arch) == false) { > + if (etm4_arch_supported(drvdata->arch >> 4) == false) { I think it would be better to simply mask out the minor version number bits in function etm4_arch_supported(). That way we can add more intelligence in there in the future if we have to and we don't have to touch the calling code again. Thanks, Mathieu > ret = -EINVAL; > goto err_arch_supported; > } > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 52786e9d8926..05d4bd330881 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -136,7 +136,7 @@ > #define ETM_MAX_RES_SEL 16 > #define ETM_MAX_SS_CMP 8 > > -#define ETM_ARCH_V4 0x40 > +#define ETM_ARCH_V4 0x4 > #define ETMv4_SYNC_MASK 0x1F > #define ETM_CYC_THRESHOLD_MASK 0xFFF > #define ETM_CYC_THRESHOLD_DEFAULT 0x100 > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/3] coresight: etm4x: Add support to enable ETMv4.2 2019-01-11 18:52 ` Mathieu Poirier @ 2019-01-12 12:33 ` saiprakash.ranjan 0 siblings, 0 replies; 16+ messages in thread From: saiprakash.ranjan @ 2019-01-12 12:33 UTC (permalink / raw) To: Mathieu Poirier Cc: Mark Rutland, devicetree, Rajendra Nayak, Suzuki K Poulose, Alexander Shishkin, linux-arm-msm, linux-kernel, David Brown, Rob Herring, Sibi Sankar, Vivek Gautam, Leo Yan, Andy Gross, linux-arm-kernel Hi Mathieu, > I think it would be better to simply mask out the minor version number > bits in > function etm4_arch_supported(). That way we can add more intelligence > in there > in the future if we have to and we don't have to touch the calling code > again. > Thanks for the review. Yes it seems good, I will make this change in next version of the patch. - Sai ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: sdm845: Remove the duplicate header inclusion 2019-01-09 17:46 [PATCH 0/3] Add coresight support for SDM845 Sai Prakash Ranjan 2019-01-09 17:46 ` [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support Sai Prakash Ranjan 2019-01-09 17:46 ` [PATCH 2/3] coresight: etm4x: Add support to enable ETMv4.2 Sai Prakash Ranjan @ 2019-01-09 17:46 ` Sai Prakash Ranjan 2019-01-09 22:57 ` Doug Anderson 2 siblings, 1 reply; 16+ messages in thread From: Sai Prakash Ranjan @ 2019-01-09 17:46 UTC (permalink / raw) To: Rob Herring, Mathieu Poirier, Suzuki K Poulose, Leo Yan, Alexander Shishkin, Andy Gross, David Brown, devicetree, Mark Rutland Cc: Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel, linux-kernel, linux-arm-msm, Sai Prakash Ranjan Remove the duplicate inclusion of qcom,gcc-sdm845.h mistakenly introduced by commit 6e17f8140521 ("arm64: dts: sdm845: add prng-ee node"). Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 03683179b8f7..8dced99f875e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -12,7 +12,6 @@ #include <dt-bindings/phy/phy-qcom-qusb2.h> #include <dt-bindings/reset/qcom,sdm845-aoss.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> -#include <dt-bindings/clock/qcom,gcc-sdm845.h> / { interrupt-parent = <&intc>; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 3/3] arm64: dts: qcom: sdm845: Remove the duplicate header inclusion 2019-01-09 17:46 ` [PATCH 3/3] arm64: dts: qcom: sdm845: Remove the duplicate header inclusion Sai Prakash Ranjan @ 2019-01-09 22:57 ` Doug Anderson 2019-01-10 4:42 ` Sai Prakash Ranjan 0 siblings, 1 reply; 16+ messages in thread From: Doug Anderson @ 2019-01-09 22:57 UTC (permalink / raw) To: Sai Prakash Ranjan, Bjorn Andersson, Andy Gross Cc: Rob Herring, Mathieu Poirier, Suzuki K Poulose, Leo Yan, Alexander Shishkin, David Brown, devicetree, Mark Rutland, Rajendra Nayak, linux-arm-msm, LKML, Sibi Sankar, Vivek Gautam, Linux ARM Hi, On Wed, Jan 9, 2019 at 9:48 AM Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> wrote: > > Remove the duplicate inclusion of qcom,gcc-sdm845.h > mistakenly introduced by commit 6e17f8140521 ("arm64: > dts: sdm845: add prng-ee node"). > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 03683179b8f7..8dced99f875e 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -12,7 +12,6 @@ > #include <dt-bindings/phy/phy-qcom-qusb2.h> > #include <dt-bindings/reset/qcom,sdm845-aoss.h> > #include <dt-bindings/soc/qcom,rpmh-rsc.h> > -#include <dt-bindings/clock/qcom,gcc-sdm845.h> This was on my TODO list, but you beat me to it. This could land any time and is completely separate from the other patches in this series. Reviewed-by: Douglas Anderson <dianders@chromium.org> ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/3] arm64: dts: qcom: sdm845: Remove the duplicate header inclusion 2019-01-09 22:57 ` Doug Anderson @ 2019-01-10 4:42 ` Sai Prakash Ranjan 0 siblings, 0 replies; 16+ messages in thread From: Sai Prakash Ranjan @ 2019-01-10 4:42 UTC (permalink / raw) To: Doug Anderson, Bjorn Andersson, Andy Gross Cc: Mark Rutland, devicetree, Rajendra Nayak, Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, linux-arm-msm, LKML, David Brown, Rob Herring, Sibi Sankar, Vivek Gautam, Leo Yan, Linux ARM Hi Doug, On 1/10/2019 4:27 AM, Doug Anderson wrote: > > This was on my TODO list, but you beat me to it. This could land any > time and is completely separate from the other patches in this series. > > Reviewed-by: Douglas Anderson <dianders@chromium.org> > Thanks for the review. Sorry I missed keeping you and Bjorn in CC. -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2019-01-18 3:00 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-01-09 17:46 [PATCH 0/3] Add coresight support for SDM845 Sai Prakash Ranjan 2019-01-09 17:46 ` [PATCH 1/3] arm64: dts: qcom: sdm845: Add Coresight support Sai Prakash Ranjan 2019-01-11 18:46 ` Mathieu Poirier 2019-01-12 12:51 ` saiprakash.ranjan 2019-01-14 15:35 ` Mathieu Poirier 2019-01-15 16:29 ` Sai Prakash Ranjan 2019-01-13 7:23 ` Bjorn Andersson 2019-01-15 16:27 ` Sai Prakash Ranjan 2019-01-17 19:50 ` Bjorn Andersson 2019-01-18 3:00 ` Sai Prakash Ranjan 2019-01-09 17:46 ` [PATCH 2/3] coresight: etm4x: Add support to enable ETMv4.2 Sai Prakash Ranjan 2019-01-11 18:52 ` Mathieu Poirier 2019-01-12 12:33 ` saiprakash.ranjan 2019-01-09 17:46 ` [PATCH 3/3] arm64: dts: qcom: sdm845: Remove the duplicate header inclusion Sai Prakash Ranjan 2019-01-09 22:57 ` Doug Anderson 2019-01-10 4:42 ` Sai Prakash Ranjan
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).