From: Catalin Marinas <catalin.marinas@arm.com>
To: Julien Thierry <julien.thierry@arm.com>
Cc: mark.rutland@arm.com, daniel.thompson@linaro.org,
Ard Biesheuvel <ard.biesheuvel@linaro.org>,
marc.zyngier@arm.com, will.deacon@arm.com,
linux-kernel@vger.kernel.org, christoffer.dall@arm.com,
james.morse@arm.com, Oleg Nesterov <oleg@redhat.com>,
joel@joelfernandes.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v8 12/26] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking
Date: Fri, 18 Jan 2019 17:33:09 +0000 [thread overview]
Message-ID: <20190118173309.GB247921@arrakis.emea.arm.com> (raw)
In-Reply-To: <20190118173002.GA247921@arrakis.emea.arm.com>
On Fri, Jan 18, 2019 at 05:30:02PM +0000, Catalin Marinas wrote:
> On Fri, Jan 18, 2019 at 04:57:32PM +0000, Julien Thierry wrote:
> > On 18/01/2019 16:09, Catalin Marinas wrote:
> > > On Tue, Jan 08, 2019 at 02:07:30PM +0000, Julien Thierry wrote:
> > >> + asm volatile(ALTERNATIVE(
> > >> + "nop",
> > >> + "mrs_s %0, " __stringify(SYS_ICC_PMR_EL1),
> > >> + ARM64_HAS_IRQ_PRIO_MASKING)
> > >> + : "=&r" (pmr)
> > >> :
> > >> : "memory");
> > >> +
> > >> + return _get_irqflags(daif_bits, pmr);
> > >> +}
> > >
> > > I find this confusing spread over two inline asm statements. IIUC, you
> > > want something like below (it could be written as inline asm but I need
> > > to understand it first):
> > >
> > > daif_bits = read_sysreg(daif);
> > >
> > > if (system_uses_irq_prio_masking()) {
> > > pmr = read_gicreg(ICC_PMR_EL1);
> > > flags = pmr & ~(daif_bits & PSR_I_BIT);
> > > } else {
> > > flags = daif_bits;
> > > }
> > >
> > > return flags;
> > >
> > > In the case where the interrupts are disabled at the PSR level, is the
> > > PMR value still relevant? Could we just return the GIC_PRIO_IRQOFF?
> > > Something like:
> > >
> > > flags = read_sysreg(daif);
> > >
> > > if (system_uses_irq_prio_masking())
> > > flags = flags & PSR_I_BIT ?
> > > GIC_PRIO_IRQOFF : read_gicreg(ICC_PMR_EL1);
> > >
> >
> > You're right, returning GIC_PRIO_IRQOFF should be good enough (it is
> > actually what happens in this version because GIC_PRIO_IRQOFF ==
> > GIC_PRIO_IRQON & ~PSR_I_BIT happens to be true).
>
> This wasn't entirely clear to me, I got confused by:
>
> + BUILD_BUG_ON(GIC_PRIO_IRQOFF < (GIC_PRIO_IRQON & ~PSR_I_BIT)); \
>
> and I thought there isn't necessarily an equality between the two.
>
> > Your suggestion would
> > make things easier to reason about. Maybe something like:
> >
> >
> > static inline unsigned long arch_local_save_flags(void)
> > {
> > unsigned long daif_bits;
> > unsigned long prio_off = GIC_PRIO_IRQOFF;
> >
> > daif_bits = read_sysreg(daif);
> >
> > asm volatile(ALTERNATIVE(
> > "mov %0, %1\n"
> > "nop\n"
> > "nop",
> > "mrs %0, SYS_ICC_PMR_EL1\n"
> > "ands %1, %1, PSR_I_BIT\n"
> > "csel %0, %0, %2, eq")
> > : "=&r" (flags)
> > : "r" (daif_bits), "r" (prio_off)
> > : "memory");
> >
> > return flags;
> > }
>
> It looks fine. If you turn the BUILD_BUG_ON into a !=, you could
> probably simplify the asm a bit (though the number of instructions
> generated would probably be the same). Untested:
>
> static inline unsigned long arch_local_save_flags(void)
> {
> unsigned long flags;
>
> flags = read_sysreg(daif);
>
> asm volatile(ALTERNATIVE(
> "nop",
> "bic %0, %1, %2")
> : "=&r" (flags)
> : "r" (flags & PSR_I_BIT), "r" (GIC_PRIO_IRQOFF)
> : "memory");
Ah, I missed a read from SYS_ICC_PMR_EL1 here. Anyway, the idea was that
you don't need to set prio_off to a variable, just pass "r" (constant)
here and the compiler does the trick.
--
Catalin
next prev parent reply other threads:[~2019-01-18 17:33 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-08 14:07 [PATCH v8 00/26] arm64: provide pseudo NMI with GICv3 Julien Thierry
2019-01-08 14:07 ` [PATCH v8 01/26] arm64: Fix HCR.TGE status for NMI contexts Julien Thierry
2019-01-14 15:56 ` Catalin Marinas
2019-01-14 16:12 ` Julien Thierry
2019-01-14 17:25 ` James Morse
2019-01-28 9:16 ` Marc Zyngier
2019-01-08 14:07 ` [PATCH v8 02/26] arm64: Remove unused daif related functions/macros Julien Thierry
2019-01-08 14:07 ` [PATCH v8 03/26] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Julien Thierry
2019-01-08 14:07 ` [PATCH v8 04/26] arm64: cpufeature: Add cpufeature for IRQ priority masking Julien Thierry
2019-01-08 14:07 ` [PATCH v8 05/26] arm/arm64: gic-v3: Add PMR and RPR accessors Julien Thierry
2019-01-08 14:07 ` [PATCH v8 06/26] irqchip/gic-v3: Switch to PMR masking before calling IRQ handler Julien Thierry
2019-01-08 14:07 ` [PATCH v8 07/26] arm64: ptrace: Provide definitions for PMR values Julien Thierry
2019-01-14 16:12 ` Catalin Marinas
2019-01-08 14:07 ` [PATCH v8 08/26] arm64: Make PMR part of task context Julien Thierry
2019-01-18 16:10 ` Catalin Marinas
2019-01-08 14:07 ` [PATCH v8 09/26] arm64: Unmask PMR before going idle Julien Thierry
2019-01-18 16:23 ` Catalin Marinas
2019-01-18 17:17 ` Julien Thierry
2019-01-08 14:07 ` [PATCH v8 10/26] arm64: kvm: Unmask PMR before entering guest Julien Thierry
2019-01-18 16:25 ` Catalin Marinas
2019-01-08 14:07 ` [PATCH v8 11/26] efi: Let architectures decide the flags that should be saved/restored Julien Thierry
2019-01-18 16:26 ` Catalin Marinas
2019-01-08 14:07 ` [PATCH v8 12/26] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Julien Thierry
2019-01-08 15:40 ` Dave Martin
2019-01-08 15:51 ` Marc Zyngier
2019-01-08 16:45 ` Dave Martin
2019-01-08 17:16 ` Marc Zyngier
2019-01-08 18:01 ` Dave Martin
2019-01-08 17:58 ` Julien Thierry
2019-01-08 18:37 ` Dave Martin
2019-01-18 16:09 ` Catalin Marinas
2019-01-18 16:57 ` Julien Thierry
2019-01-18 17:30 ` Catalin Marinas
2019-01-18 17:33 ` Catalin Marinas [this message]
2019-01-21 8:45 ` Julien Thierry
2019-01-18 16:35 ` Dave Martin
2019-01-18 17:27 ` Julien Thierry
2019-01-18 18:23 ` Dave Martin
2019-01-08 14:07 ` [PATCH v8 13/26] arm64: daifflags: Include PMR in daifflags restore operations Julien Thierry
2019-01-18 16:43 ` Catalin Marinas
2019-01-08 14:07 ` [PATCH v8 14/26] arm64: alternative: Allow alternative status checking per cpufeature Julien Thierry
2019-01-08 14:07 ` [PATCH v8 15/26] arm64: alternative: Apply alternatives early in boot process Julien Thierry
2019-01-08 14:51 ` Suzuki K Poulose
2019-01-08 15:20 ` Julien Thierry
2019-01-08 17:40 ` Suzuki K Poulose
2019-01-10 10:50 ` Julien Thierry
2019-01-08 14:07 ` [PATCH v8 16/26] irqchip/gic-v3: Factor group0 detection into functions Julien Thierry
2019-01-08 14:07 ` [PATCH v8 17/26] arm64: Switch to PMR masking when starting CPUs Julien Thierry
2019-01-08 14:07 ` [PATCH v8 18/26] arm64: gic-v3: Implement arch support for priority masking Julien Thierry
2019-01-08 14:07 ` [PATCH v8 19/26] irqchip/gic-v3: Detect if GIC can support pseudo-NMIs Julien Thierry
2019-01-08 14:07 ` [PATCH v8 20/26] irqchip/gic-v3: Handle pseudo-NMIs Julien Thierry
2019-01-08 14:07 ` [PATCH v8 21/26] irqchip/gic: Add functions to access irq priorities Julien Thierry
2019-01-08 14:07 ` [PATCH v8 22/26] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Julien Thierry
2019-01-08 14:07 ` [PATCH v8 23/26] arm64: Handle serror in NMI context Julien Thierry
2019-01-08 14:07 ` [PATCH v8 24/26] arm64: Skip preemption when exiting an NMI Julien Thierry
2019-01-08 14:07 ` [PATCH v8 25/26] arm64: Skip irqflags tracing for NMI in IRQs disabled context Julien Thierry
2019-01-08 14:07 ` [PATCH v8 26/26] arm64: Enable the support of pseudo-NMIs Julien Thierry
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