From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 251A2C31D63 for ; Mon, 21 Jan 2019 07:23:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E710020823 for ; Mon, 21 Jan 2019 07:23:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728347AbfAUHXd (ORCPT ); Mon, 21 Jan 2019 02:23:33 -0500 Received: from shell.v3.sk ([90.176.6.54]:49544 "EHLO shell.v3.sk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728222AbfAUHXd (ORCPT ); Mon, 21 Jan 2019 02:23:33 -0500 Received: from localhost (localhost [127.0.0.1]) by zimbra.v3.sk (Postfix) with ESMTP id E8824CAE29; Mon, 21 Jan 2019 07:03:56 +0100 (CET) Received: from shell.v3.sk ([127.0.0.1]) by localhost (zimbra.v3.sk [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id 5IVA6vgqZbOq; Mon, 21 Jan 2019 07:03:53 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by zimbra.v3.sk (Postfix) with ESMTP id 07B01CAE2A; Mon, 21 Jan 2019 07:03:53 +0100 (CET) X-Virus-Scanned: amavisd-new at zimbra.v3.sk Received: from shell.v3.sk ([127.0.0.1]) by localhost (zimbra.v3.sk [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id xZYBKZF4kRF2; Mon, 21 Jan 2019 07:03:52 +0100 (CET) Received: from belphegor.brq.redhat.com (nat-pool-brq-t.redhat.com [213.175.37.10]) by zimbra.v3.sk (Postfix) with ESMTPSA id D1218CAE29; Mon, 21 Jan 2019 07:03:51 +0100 (CET) From: Lubomir Rintel To: Russell King Cc: David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Lubomir Rintel Subject: [PATCH] drm/armada: add mmp2 support Date: Mon, 21 Jan 2019 07:03:49 +0100 Message-Id: <20190121060349.549797-1-lkundrak@v3.sk> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Heavily based on the Armada 510 (Dove) support. Like with 510 support, th= is also just supports a single source clock -- the "Display 1" clock as generated by the APMU. This one was chosen because the OLPC XO 1.75 lapto= p uses it for its internal panel. If anyone uses this to drive a MIPI or HDMI encoder, they may want to extend this to choose a different source for the pixel clock -- it should be a reasonably straightforward thing to do. The data sheet is not available, but James Cameron of OLPC kindly provided some details about the LCD_SCLK_DIV register. Link: https://lists.freedesktop.org/archives/dri-devel/2018-December/2010= 21.html Signed-off-by: Lubomir Rintel --- drivers/gpu/drm/armada/Makefile | 1 + drivers/gpu/drm/armada/armada_610.c | 93 ++++++++++++++++++++++++++++ drivers/gpu/drm/armada/armada_crtc.c | 4 ++ drivers/gpu/drm/armada/armada_drm.h | 1 + drivers/gpu/drm/armada/armada_hw.h | 10 +++ 5 files changed, 109 insertions(+) create mode 100644 drivers/gpu/drm/armada/armada_610.c diff --git a/drivers/gpu/drm/armada/Makefile b/drivers/gpu/drm/armada/Mak= efile index 9bc3c3213724..5bbf86324cda 100644 --- a/drivers/gpu/drm/armada/Makefile +++ b/drivers/gpu/drm/armada/Makefile @@ -2,6 +2,7 @@ armada-y :=3D armada_crtc.o armada_drv.o armada_fb.o armada_fbdev.o \ armada_gem.o armada_overlay.o armada_plane.o armada_trace.o armada-y +=3D armada_510.o +armada-y +=3D armada_610.o armada-$(CONFIG_DEBUG_FS) +=3D armada_debugfs.o =20 obj-$(CONFIG_DRM_ARMADA) :=3D armada.o diff --git a/drivers/gpu/drm/armada/armada_610.c b/drivers/gpu/drm/armada= /armada_610.c new file mode 100644 index 000000000000..278b204038ea --- /dev/null +++ b/drivers/gpu/drm/armada/armada_610.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012 Russell King + * Copyright (C) 2018,2019 Lubomir Rintel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Armada MMP2 variant support + */ +#include +#include +#include +#include "armada_crtc.h" +#include "armada_drm.h" +#include "armada_hw.h" + +static int armada610_crtc_init(struct armada_crtc *dcrtc, struct device = *dev) +{ + struct clk *clk; + + clk =3D devm_clk_get(dev, "disp0"); + if (IS_ERR(clk)) + return PTR_ERR(clk) =3D=3D -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk); + + dcrtc->extclk[0] =3D clk; + + return 0; +} + +/* + * This gets called with sclk =3D NULL to test whether the mode is + * supportable, and again with sclk !=3D NULL to set the clocks up for + * that. The former can return an error, but the latter is expected + * not to. + */ +static int armada610_crtc_compute_clock(struct armada_crtc *dcrtc, + const struct drm_display_mode *mode, uint32_t *sclk) +{ + struct clk *clk =3D dcrtc->extclk[0]; + uint32_t ret, rate, ref, div; + + if (IS_ERR(clk)) + return PTR_ERR(clk); + + rate =3D mode->clock * 1000; + ref =3D clk_get_rate(clk); + div =3D DIV_ROUND_UP(ref, rate); + + if (div < 2) + return -EINVAL; + + if (dcrtc->clk !=3D clk) { + ret =3D clk_prepare_enable(clk); + if (ret) + return ret; + dcrtc->clk =3D clk; + } + + if (sclk) { + *sclk =3D 0x00001000; /* No idea */ + *sclk |=3D 1 << 8; /* MIPI clock bypass */ + *sclk |=3D SCLK_610_DISP0; + *sclk |=3D div; + } + + return 0; +} + +static void armada610_crtc_disable(struct armada_crtc *dcrtc) +{ + if (!IS_ERR(dcrtc->clk)) { + clk_disable_unprepare(dcrtc->clk); + dcrtc->clk =3D ERR_PTR(-EINVAL); + } +} + +static void armada610_crtc_enable(struct armada_crtc *dcrtc, + const struct drm_display_mode *mode) +{ + if (IS_ERR(dcrtc->clk)) { + dcrtc->clk =3D dcrtc->extclk[0]; + WARN_ON(clk_prepare_enable(dcrtc->clk)); + } +} + +const struct armada_variant armada610_ops =3D { + .init =3D armada610_crtc_init, + .compute_clock =3D armada610_crtc_compute_clock, + .disable =3D armada610_crtc_disable, + .enable =3D armada610_crtc_enable, +}; diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armad= a/armada_crtc.c index da9360688b55..927be8898eb7 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -884,6 +884,10 @@ static const struct of_device_id armada_lcd_of_match= [] =3D { .compatible =3D "marvell,dove-lcd", .data =3D &armada510_ops, }, + { + .compatible =3D "marvell,mmp2-lcd", + .data =3D &armada610_ops, + }, {} }; MODULE_DEVICE_TABLE(of, armada_lcd_of_match); diff --git a/drivers/gpu/drm/armada/armada_drm.h b/drivers/gpu/drm/armada= /armada_drm.h index f09083ff15d3..7cbcf33d0304 100644 --- a/drivers/gpu/drm/armada/armada_drm.h +++ b/drivers/gpu/drm/armada/armada_drm.h @@ -52,6 +52,7 @@ struct armada_variant { =20 /* Variant ops */ extern const struct armada_variant armada510_ops; +extern const struct armada_variant armada610_ops; =20 struct armada_private { struct drm_device drm; diff --git a/drivers/gpu/drm/armada/armada_hw.h b/drivers/gpu/drm/armada/= armada_hw.h index 277580b36758..df2ff77b9c07 100644 --- a/drivers/gpu/drm/armada/armada_hw.h +++ b/drivers/gpu/drm/armada/armada_hw.h @@ -205,6 +205,16 @@ enum { SCLK_510_FRAC_DIV_MASK =3D 0xfff << 16, SCLK_510_INT_DIV_MASK =3D 0xffff << 0, =20 + /* Armada 610 */ + SCLK_610_AXI =3D 0x0 << 30, + SCLK_610_DISP0 =3D 0x1 << 30, /* LCD Display 1 */ + SCLK_610_DISP1 =3D 0x2 << 30, /* LCD Display 2 */ + SCLK_610_PLL =3D 0x3 << 30, /* HDMI PLL clock */ + SCLK_610_PANEL_CLK_DIS =3D 0x1 << 28, /* 1 =3D panel clock disabled */ + SCLK_610_FRAC_DIV_MASK =3D 0xfff << 16, + SCLK_610_MIPI_DIV_MASK =3D 0xf << 8, /* 0 =3D off, 1 =3D bypass, ... */ + SCLK_610_INT_DIV_MASK =3D 0xff << 0, + /* Armada 16x */ SCLK_16X_AHB =3D 0x0 << 28, SCLK_16X_PCLK =3D 0x1 << 28, --=20 2.20.1