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Tue, 22 Jan 2019 11:10:48 +0000 From: "james qian wang (Arm Technology China)" To: Liviu Dudau , "airlied@linux.ie" , Brian Starkey CC: "Jonathan Chai (Arm Technology China)" , "Julien Yin (Arm Technology China)" , "thomas Sun (Arm Technology China)" , "Lowry Li (Arm Technology China)" , Ayan Halder , "Tiannan Zhu (Arm Technology China)" , "Jin Gao (Arm Technology China)" , "Yiqi Kang (Arm Technology China)" , nd , "malidp@foss.arm.com" , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "james qian wang (Arm Technology China)" Subject: [PATCH v2 03/11] drm/komeda: Add komeda_crtc_atomic_flush Thread-Topic: [PATCH v2 03/11] drm/komeda: Add komeda_crtc_atomic_flush Thread-Index: AQHUskMgVWflZN1Mf0+iLzifEy0HzA== Date: Tue, 22 Jan 2019 11:10:48 +0000 Message-ID: <20190122110932.5138-4-james.qian.wang@arm.com> References: <20190122110932.5138-1-james.qian.wang@arm.com> In-Reply-To: <20190122110932.5138-1-james.qian.wang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [113.29.88.7] x-clientproxiedby: SYAPR01CA0034.ausprd01.prod.outlook.com (2603:10c6:1:1::22) To DB6PR0801MB1990.eurprd08.prod.outlook.com (2603:10a6:4:6c::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=james.qian.wang@arm.com; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: ab6c4ae3-5bea-4bfb-0af5-08d6805a4337 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Jan 2019 11:10:40.1814 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0801MB1286 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "james qian wang (Arm Technology China)" A komeda flush is comprised two steps: 1. update pipeline/component state to HW. 2. call dev_func->flush to notify HW to kickoff the update. Signed-off-by: James Qian Wang (Arm Technology China) --- .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 11 ++++++ .../gpu/drm/arm/display/komeda/komeda_crtc.c | 33 +++++++++++++++++ .../gpu/drm/arm/display/komeda/komeda_dev.h | 3 ++ .../drm/arm/display/komeda/komeda_pipeline.h | 5 +++ .../display/komeda/komeda_pipeline_state.c | 37 +++++++++++++++++++ 5 files changed, 89 insertions(+) diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c b/drivers/gpu= /drm/arm/display/komeda/d71/d71_dev.c index afc13d3b3afc..74aab4f23ea0 100644 --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c @@ -241,6 +241,16 @@ static int d71_disable_irq(struct komeda_dev *mdev) return 0; } =20 +static void d71_flush(struct komeda_dev *mdev, + int master_pipe, u32 active_pipes) +{ + struct d71_dev *d71 =3D mdev->chip_data; + u32 reg_offset =3D (master_pipe =3D=3D 0) ? + GCU_CONFIG_VALID0 : GCU_CONFIG_VALID1; + + malidp_write32(d71->gcu_addr, reg_offset, GCU_CONFIG_CVAL); +} + static int d71_reset(struct d71_dev *d71) { u32 __iomem *gcu =3D d71->gcu_addr; @@ -457,6 +467,7 @@ static struct komeda_dev_funcs d71_chip_funcs =3D { .irq_handler =3D d71_irq_handler, .enable_irq =3D d71_enable_irq, .disable_irq =3D d71_disable_irq, + .flush =3D d71_flush, }; =20 struct komeda_dev_funcs * diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu= /drm/arm/display/komeda/komeda_crtc.c index a250ab824155..95d8f2bcd523 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -58,8 +58,41 @@ void komeda_crtc_handle_event(struct komeda_crtc *kcrt= c, DRM_DEBUG("FLIP Done.\n"); } =20 +static void +komeda_crtc_do_flush(struct drm_crtc *crtc, + struct drm_crtc_state *old) +{ + struct komeda_crtc *kcrtc =3D to_kcrtc(crtc); + struct komeda_crtc_state *kcrtc_st =3D to_kcrtc_st(crtc->state); + struct komeda_dev *mdev =3D kcrtc->base.dev->dev_private; + struct komeda_pipeline *master =3D kcrtc->master; + + DRM_DEBUG_ATOMIC("CRTC%d_FLUSH: active_pipes: 0x%x, affected: 0x%x.\n", + drm_crtc_index(crtc), + kcrtc_st->active_pipes, kcrtc_st->affected_pipes); + + /* step 1: update the pipeline/component state to HW */ + if (has_bit(master->id, kcrtc_st->affected_pipes)) + komeda_pipeline_update(master, old->state); + + /* step 2: notify the HW to kickoff the update */ + mdev->funcs->flush(mdev, master->id, kcrtc_st->active_pipes); +} + +static void +komeda_crtc_atomic_flush(struct drm_crtc *crtc, + struct drm_crtc_state *old) +{ + /* commit with modeset will be handled in enable/disable */ + if (drm_atomic_crtc_needs_modeset(crtc->state)) + return; + + komeda_crtc_do_flush(crtc, old); +} + struct drm_crtc_helper_funcs komeda_crtc_helper_funcs =3D { .atomic_check =3D komeda_crtc_atomic_check, + .atomic_flush =3D komeda_crtc_atomic_flush, }; =20 static const struct drm_crtc_funcs komeda_crtc_funcs =3D { diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h b/drivers/gpu/= drm/arm/display/komeda/komeda_dev.h index 8eae2620ce77..0bd38bdf0518 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h @@ -106,6 +106,9 @@ struct komeda_dev_funcs { =20 /** @dump_register: Optional, dump registers to seq_file */ void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq); + /** @flush: Notify the HW to flush or kickoff the update */ + void (*flush)(struct komeda_dev *mdev, + int master_pipe, u32 active_pipes); }; =20 /** diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h b/drivers= /gpu/drm/arm/display/komeda/komeda_pipeline.h index 54b646128760..3d7a9ee550b2 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h @@ -412,4 +412,9 @@ int komeda_build_display_data_flow(struct komeda_crtc *= kcrtc, int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe, struct komeda_crtc_state *kcrtc_st); =20 +void komeda_pipeline_disable(struct komeda_pipeline *pipe, + struct drm_atomic_state *old_state); +void komeda_pipeline_update(struct komeda_pipeline *pipe, + struct drm_atomic_state *old_state); + #endif /* _KOMEDA_PIPELINE_H_*/ diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/d= rivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c index 6797be630529..87fd6493d202 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c @@ -31,6 +31,18 @@ komeda_pipeline_get_state(struct komeda_pipeline *pipe, return priv_to_pipe_st(priv_st); } =20 +struct komeda_pipeline_state * +komeda_pipeline_get_old_state(struct komeda_pipeline *pipe, + struct drm_atomic_state *state) +{ + struct drm_private_state *priv_st; + + priv_st =3D drm_atomic_get_old_private_obj_state(state, &pipe->obj); + if (priv_st) + return priv_to_pipe_st(priv_st); + return NULL; +} + struct komeda_pipeline_state * komeda_pipeline_get_new_state(struct komeda_pipeline *pipe, struct drm_atomic_state *state) @@ -536,3 +548,28 @@ int komeda_release_unclaimed_resources(struct komeda_p= ipeline *pipe, =20 return 0; } + +void komeda_pipeline_update(struct komeda_pipeline *pipe, + struct drm_atomic_state *old_state) +{ + struct komeda_pipeline_state *new =3D priv_to_pipe_st(pipe->obj.state); + struct komeda_pipeline_state *old; + struct komeda_component *c; + u32 id, changed_comps =3D 0; + + old =3D komeda_pipeline_get_old_state(pipe, old_state); + + changed_comps =3D new->active_comps | old->active_comps; + + DRM_DEBUG_ATOMIC("PIPE%d: active_comps: 0x%x, changed: 0x%x.\n", + pipe->id, new->active_comps, changed_comps); + + dp_for_each_set_bit(id, changed_comps) { + c =3D komeda_pipeline_get_component(pipe, id); + + if (new->active_comps & BIT(c->id)) + c->funcs->update(c, priv_to_comp_st(c->obj.state)); + else + c->funcs->disable(c); + } +} --=20 2.17.1