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Tue, 22 Jan 2019 11:11:07 +0000 From: "james qian wang (Arm Technology China)" To: Liviu Dudau , "airlied@linux.ie" , Brian Starkey CC: "Jonathan Chai (Arm Technology China)" , "Julien Yin (Arm Technology China)" , "thomas Sun (Arm Technology China)" , "Lowry Li (Arm Technology China)" , Ayan Halder , "Tiannan Zhu (Arm Technology China)" , "Jin Gao (Arm Technology China)" , "Yiqi Kang (Arm Technology China)" , nd , "malidp@foss.arm.com" , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "james qian wang (Arm Technology China)" Subject: [PATCH v2 05/11] drm/komeda: Add komeda_crtc_prepare/unprepare Thread-Topic: [PATCH v2 05/11] drm/komeda: Add komeda_crtc_prepare/unprepare Thread-Index: AQHUskMsibovwpzi6E6Ub38r7bWMsw== Date: Tue, 22 Jan 2019 11:11:07 +0000 Message-ID: <20190122110932.5138-6-james.qian.wang@arm.com> References: <20190122110932.5138-1-james.qian.wang@arm.com> In-Reply-To: <20190122110932.5138-1-james.qian.wang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [113.29.88.7] x-clientproxiedby: SYAPR01CA0034.ausprd01.prod.outlook.com (2603:10c6:1:1::22) To DB6PR0801MB1990.eurprd08.prod.outlook.com (2603:10a6:4:6c::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=james.qian.wang@arm.com; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 40e348af-74b7-478f-b995-08d6805a4de5 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Jan 2019 11:10:58.1034 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0801MB1784 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "james qian wang (Arm Technology China)" These two function will be used by komeda_crtc_enable/disable to do some prepartion works when enable/disable a crtc. like enable a crtc: 1. Adjust display operation mode. 2. Enable/prepare needed clk. v2: Rebase Signed-off-by: James Qian Wang (Arm Technology China) --- .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 32 ++++++ .../gpu/drm/arm/display/komeda/komeda_crtc.c | 104 ++++++++++++++++++ .../gpu/drm/arm/display/komeda/komeda_dev.c | 2 + .../gpu/drm/arm/display/komeda/komeda_dev.h | 26 +++++ 4 files changed, 164 insertions(+) diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c b/drivers/gpu= /drm/arm/display/komeda/d71/d71_dev.c index 74aab4f23ea0..2fb29aea9f69 100644 --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c @@ -241,6 +241,37 @@ static int d71_disable_irq(struct komeda_dev *mdev) return 0; } =20 +static int to_d71_opmode(int core_mode) +{ + switch (core_mode) { + case KOMEDA_MODE_DISP0: + return DO0_ACTIVE_MODE; + case KOMEDA_MODE_DISP1: + return DO1_ACTIVE_MODE; + case KOMEDA_MODE_DUAL_DISP: + return DO01_ACTIVE_MODE; + case KOMEDA_MODE_INACTIVE: + return INACTIVE_MODE; + default: + WARN(1, "Unknown operation mode"); + return INACTIVE_MODE; + } +} + +static int d71_change_opmode(struct komeda_dev *mdev, int new_mode) +{ + struct d71_dev *d71 =3D mdev->chip_data; + u32 opmode =3D to_d71_opmode(new_mode); + int ret; + + malidp_write32_mask(d71->gcu_addr, BLK_CONTROL, 0x7, opmode); + + ret =3D dp_wait_cond(((malidp_read32(d71->gcu_addr, BLK_CONTROL) & 0x7) = =3D=3D opmode), + 100, 1000, 10000); + + return ret > 0 ? 0 : -ETIMEDOUT; +} + static void d71_flush(struct komeda_dev *mdev, int master_pipe, u32 active_pipes) { @@ -467,6 +498,7 @@ static struct komeda_dev_funcs d71_chip_funcs =3D { .irq_handler =3D d71_irq_handler, .enable_irq =3D d71_enable_irq, .disable_irq =3D d71_disable_irq, + .change_opmode =3D d71_change_opmode, .flush =3D d71_flush, }; =20 diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu= /drm/arm/display/komeda/komeda_crtc.c index 7e0bf78da733..ef4c3ee2a688 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -40,6 +40,110 @@ komeda_crtc_atomic_check(struct drm_crtc *crtc, return 0; } =20 +u32 komeda_calc_mclk(struct komeda_crtc_state *kcrtc_st) +{ + unsigned long mclk =3D kcrtc_st->base.adjusted_mode.clock * 1000; + + return mclk; +} + +/* For active a crtc, mainly need two parts of preparation + * 1. adjust display operation mode. + * 2. enable needed clk + */ +int +komeda_crtc_prepare(struct komeda_crtc *kcrtc) +{ + struct komeda_dev *mdev =3D kcrtc->base.dev->dev_private; + struct komeda_pipeline *master =3D kcrtc->master; + struct komeda_crtc_state *kcrtc_st =3D to_kcrtc_st(kcrtc->base.state); + unsigned long pxlclk_rate =3D kcrtc_st->base.adjusted_mode.clock * 1000; + u32 new_mode; + int err; + + mutex_lock(&mdev->lock); + + new_mode =3D mdev->dpmode | BIT(master->id); + if (WARN_ON(new_mode =3D=3D mdev->dpmode)) { + err =3D 0; + goto unlock; + } + + err =3D mdev->funcs->change_opmode(mdev, new_mode); + if (err) { + DRM_ERROR("failed to change opmode: 0x%x -> 0x%x.\n,", + mdev->dpmode, new_mode); + goto unlock; + } + + mdev->dpmode =3D new_mode; + /* Only need to enable mclk on single display mode, but no need to + * enable mclk it on dual display mode, since the dual mode always + * switch from single display mode, the mclk already enabled, no need + * to enable it again. + */ + if (new_mode !=3D KOMEDA_MODE_DUAL_DISP) { + err =3D clk_set_rate(mdev->mclk, komeda_calc_mclk(kcrtc_st)); + if (err) + DRM_ERROR("failed to set mclk.\n"); + err =3D clk_prepare_enable(mdev->mclk); + if (err) + DRM_ERROR("failed to enable mclk.\n"); + } + + err =3D clk_prepare_enable(master->aclk); + if (err) + DRM_ERROR("failed to enable axi clk for pipe%d.\n", master->id); + err =3D clk_set_rate(master->pxlclk, pxlclk_rate); + if (err) + DRM_ERROR("failed to set pxlclk for pipe%d\n", master->id); + err =3D clk_prepare_enable(master->pxlclk); + if (err) + DRM_ERROR("failed to enable pxl clk for pipe%d.\n", master->id); + +unlock: + mutex_unlock(&mdev->lock); + + return err; +} + +int +komeda_crtc_unprepare(struct komeda_crtc *kcrtc) +{ + struct komeda_dev *mdev =3D kcrtc->base.dev->dev_private; + struct komeda_pipeline *master =3D kcrtc->master; + u32 new_mode; + int err; + + mutex_lock(&mdev->lock); + + new_mode =3D mdev->dpmode & (~BIT(master->id)); + + if (WARN_ON(new_mode =3D=3D mdev->dpmode)) { + err =3D 0; + goto unlock; + } + + err =3D mdev->funcs->change_opmode(mdev, new_mode); + if (err) { + DRM_ERROR("failed to change opmode: 0x%x -> 0x%x.\n,", + mdev->dpmode, new_mode); + goto unlock; + } + + mdev->dpmode =3D new_mode; + + clk_disable_unprepare(master->pxlclk); + clk_disable_unprepare(master->aclk); + if (new_mode =3D=3D KOMEDA_MODE_INACTIVE) + clk_disable_unprepare(mdev->mclk); + +unlock: + mutex_unlock(&mdev->lock); + + return err; +} + void komeda_crtc_handle_event(struct komeda_crtc *kcrtc, struct komeda_events *evts) { diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.c b/drivers/gpu/= drm/arm/display/komeda/komeda_dev.c index a012b3bbf53b..7152f2c08e01 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.c @@ -145,6 +145,8 @@ struct komeda_dev *komeda_dev_create(struct device *dev= ) if (!mdev) return ERR_PTR(-ENOMEM); =20 + mutex_init(&mdev->lock); + mdev->dev =3D dev; mdev->reg_base =3D devm_ioremap_resource(dev, io_res); if (IS_ERR(mdev->reg_base)) { diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h b/drivers/gpu/= drm/arm/display/komeda/komeda_dev.h index 0bd38bdf0518..1ad1f6e49854 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h @@ -106,11 +106,34 @@ struct komeda_dev_funcs { =20 /** @dump_register: Optional, dump registers to seq_file */ void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq); + /** + * @change_opmode: + * + * Notify HW to switch to a new display operation mode. + */ + int (*change_opmode)(struct komeda_dev *mdev, int new_mode); /** @flush: Notify the HW to flush or kickoff the update */ void (*flush)(struct komeda_dev *mdev, int master_pipe, u32 active_pipes); }; =20 +/** + * DISPLAY_MODE describes how many display been enabled, and which will be + * passed to CHIP by &komeda_dev_funcs->change_opmode(), then CHIP can do = the + * pipeline resources assignment according to this usage hint. + * - KOMEDA_MODE_DISP0: Only one display enabled, pipeline-0 work as mas= ter. + * - KOMEDA_MODE_DISP1: Only one display enabled, pipeline-0 work as mas= ter. + * - KOMEDA_MODE_DUAL_DISP: Dual display mode, both display has been ena= bled. + * And D71 supports assign two pipelines to one single display on mode + * KOMEDA_MODE_DISP0/DISP1 + */ +enum { + KOMEDA_MODE_INACTIVE =3D 0, + KOMEDA_MODE_DISP0 =3D BIT(0), + KOMEDA_MODE_DISP1 =3D BIT(1), + KOMEDA_MODE_DUAL_DISP =3D KOMEDA_MODE_DISP0 | KOMEDA_MODE_DISP1, +}; + /** * struct komeda_dev * @@ -133,6 +156,9 @@ struct komeda_dev { /** @irq: irq number */ int irq; =20 + struct mutex lock; /* used to protect dpmode */ + u32 dpmode; /* current display mode */ + int n_pipelines; struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES]; =20 --=20 2.17.1