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* [PATCH v2 0/9] phy: qcom-ufs: Enable regulators to be off in suspend
@ 2019-01-23 22:11 Evan Green
  2019-01-23 22:11 ` [PATCH v2 1/9] dt-bindings: ufs: Add #reset-cells for Qualcomm controllers Evan Green
                   ` (8 more replies)
  0 siblings, 9 replies; 20+ messages in thread
From: Evan Green @ 2019-01-23 22:11 UTC (permalink / raw)
  To: Andy Gross, Rob Herring, Kishon Vijay Abraham I
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Stephen Boyd,
	Vivek Gautam, Evan Green, Bjorn Andersson, Arnd Bergmann,
	Grygorii Strashko, Vinayak Holikatti, Jeffrey Hugo, linux-scsi,
	David Brown, James E.J. Bottomley, devicetree, liwei,
	Marc Gonzalez, linux-arm-msm, Martin K. Petersen, linux-kernel,
	Manu Gautam, Mark Rutland, Subhash Jadavani

The goal with this series is to enable shutting off regulators that power
UFS during system suspend.

In "the good life" version of this, we'd just disable the regulators
in phy_poweroff and be done with it. Unfortunately, that's not symmetric,
as regulators are not enabled during phy_poweron. Ok, so you might think
we could just move the regulator enable and anything else that needs to
come along into phy_poweron, so that we can then undo it all in
phy_poweroff. That's where things get tricky.

The qcom-qmp-phy overloaded the phy_init and phy_poweron callbacks,
basically to mean "init phase 1" and "init phase 2". There are two phases
because they have this phy_reset bit outside of the phy (in the UFS
controller registers), and they need to make sure this bit is toggled at
specific points in the phy init sequence. So there's this implicit
sequence in the init dance between ufs-qcom.c and phy-qcom-qmp.c:
1) ufs-qcom asserts the PHY reset bit.
2) phy-qcom-qmp phy_init does most of its initialization, but exits early.
3) ufs-qcom deasserts the PHY reset bit.
4) phy-qcom-qmp phy_poweron finishes its initialization.

This init dance is very difficult to follow in the code (since it's split
between two drivers and not spelled out well), and arguably represents a
deficiency in the hardware description of these devices.

In this series I'm proposing tweaking the bindings for the Qualcomm
UFS controller and PHY. In it we expose a reset controller from the
UFS controller, that is then picked up and used from the PHY code.
With this, the phy code can be reorganized to complete its initialization
in a single function, removing the implicit two-phase overloading.

Then I can move most of the phy initialization, including enabling
the regulators, into phy_poweron. Now, when phy_poweroff is called,
the phy actually powers off. This finally disables the regulators
and allows me to save power in system suspend.

Because the UFS PHY reset bit is now toggled in the PHY, rather
than in ufs-qcom, this also percolated to all other PHYs using
ufs-qcom, which from what I can see is just 8996.

There are a couple of tradeoffs in this series that I'd welcome feedback
on. First, it breaks compatibility with device trees that don't expose
this new reset controller. Making this work with older device trees
would be pretty ugly in the code, and given that the SDM845 UFS DT nodes
aren't accepted upstream yet, the breakage seemed worth it. I'm not as
sure about 8996.

Second, I removed the calls to phy_poweroff during clock gating. This
was originally dialing down a clock or two, while leaving the phy powered.
I've now changed the semantics of phy_poweroff to, well, actually power off.
This works great for userlands that have set UFS's spm_lvl to 5 (off) like
I have, but maybe changes power consumption for devices that have spm_lvl
set to 3. I could try to use phy_init and phy_poweron as the two different
possible transitions (fully off, and clocks off respectively), but I'm not
sure if it actually matters, and I like the idea that phy_poweroff really
does power the thing off.

Also, I don't have an 8996 device to test. If someone is able to test this
out and perhaps point out any (hopefully obvious) bugs in the 8996 portion,
I'd be grateful.

This patch is based atop phy-next, plus the UFS DT nodes, which are now
patch 3, 4, 5 of [1].

[1] https://lore.kernel.org/lkml/20181210192826.241350-1-evgreen@chromium.org/

Changes in v2:
- Added resets to example (Stephen).
- Remove include of reset.h (Stephen)
- Fix error print of phy_power_on (Stephen)
- Comment for reset controller warnings on id != 0 (Stephen)
- Add static to ufs_qcom_reset_ops (Stephen).
- Use devm_* to get the reset (Stephen)
- Clear ufs_reset on error getting it
- Remove needless error print (Stephen)
- Removed whitespace changes (Stephen)
- Use devm_ to get the reset (Stephen)

Evan Green (9):
  dt-bindings: ufs: Add #reset-cells for Qualcomm controllers
  dt-bindings: phy-qcom-qmp: Add UFS PHY reset
  dt-bindings: phy: qcom-ufs: Add resets property
  arm64: dts: sdm845: Add UFS PHY reset
  arm64: dts: msm8996: Add UFS PHY reset controller
  scsi: ufs: qcom: Expose the reset controller for PHY
  phy: qcom-qmp: Utilize UFS reset controller
  phy: qcom-qmp: Move UFS phy to phy_poweron/off
  phy: qcom-ufs: Refactor all init steps into phy_poweron

 .../devicetree/bindings/phy/qcom-qmp-phy.txt  |   6 +-
 .../devicetree/bindings/ufs/ufs-qcom.txt      |   5 +-
 .../devicetree/bindings/ufs/ufshcd-pltfrm.txt |   3 +
 arch/arm64/boot/dts/qcom/msm8996.dtsi         |   4 +-
 arch/arm64/boot/dts/qcom/sdm845.dtsi          |   3 +
 drivers/phy/qualcomm/phy-qcom-qmp.c           | 122 ++++++++++--------
 drivers/phy/qualcomm/phy-qcom-ufs-i.h         |   5 +-
 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c  |  25 +---
 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c  |  25 +---
 drivers/phy/qualcomm/phy-qcom-ufs.c           |  57 ++++++--
 drivers/scsi/ufs/Kconfig                      |   1 +
 drivers/scsi/ufs/ufs-qcom.c                   | 111 +++++++++-------
 drivers/scsi/ufs/ufs-qcom.h                   |   4 +
 13 files changed, 204 insertions(+), 167 deletions(-)

-- 
2.18.1


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v2 1/9] dt-bindings: ufs: Add #reset-cells for Qualcomm controllers
  2019-01-23 22:11 [PATCH v2 0/9] phy: qcom-ufs: Enable regulators to be off in suspend Evan Green
@ 2019-01-23 22:11 ` Evan Green
  2019-01-30 18:56   ` Rob Herring
  2019-02-01 17:41   ` Stephen Boyd
  2019-01-23 22:11 ` [PATCH v2 2/9] dt-bindings: phy-qcom-qmp: Add UFS PHY reset Evan Green
                   ` (7 subsequent siblings)
  8 siblings, 2 replies; 20+ messages in thread
From: Evan Green @ 2019-01-23 22:11 UTC (permalink / raw)
  To: Andy Gross, Rob Herring, Kishon Vijay Abraham I
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Stephen Boyd,
	Vivek Gautam, Evan Green, devicetree, liwei, linux-kernel,
	Subhash Jadavani, Martin K. Petersen, Mark Rutland

Enable Qualcomm UFS controllers to expose the PHY reset via a reset
controller.

Signed-off-by: Evan Green <evgreen@chromium.org>

---
Fixing up this aspect of it made me notice that this patch [1]
hasn't landed yet. It really ought to.

[1] https://lore.kernel.org/lkml/20181012213926.253765-1-dianders@chromium.org/T/#u

Changes in v2: None

 Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
index 8cf59452c6756..e2460b666ae45 100644
--- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
+++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
@@ -47,6 +47,8 @@ Optional properties:
 -lanes-per-direction	: number of lanes available per direction - either 1 or 2.
 			  Note that it is assume same number of lanes is used both
 			  directions at once. If not specified, default is 2 lanes per direction.
+- #reset-cells		: Must be <1> for Qualcomm UFS controllers that expose
+			  PHY reset from the UFS controller.
 - resets            : reset node register
 - reset-names       : describe reset node register, the "rst" corresponds to reset the whole UFS IP.
 
@@ -76,4 +78,5 @@ Example:
 		reset-names = "rst";
 		phys = <&ufsphy1>;
 		phy-names = "ufsphy";
+		#reset-cells = <1>;
 	};
-- 
2.18.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 2/9] dt-bindings: phy-qcom-qmp: Add UFS PHY reset
  2019-01-23 22:11 [PATCH v2 0/9] phy: qcom-ufs: Enable regulators to be off in suspend Evan Green
  2019-01-23 22:11 ` [PATCH v2 1/9] dt-bindings: ufs: Add #reset-cells for Qualcomm controllers Evan Green
@ 2019-01-23 22:11 ` Evan Green
  2019-02-01 17:41   ` Stephen Boyd
  2019-01-23 22:11 ` [PATCH v2 3/9] dt-bindings: phy: qcom-ufs: Add resets property Evan Green
                   ` (6 subsequent siblings)
  8 siblings, 1 reply; 20+ messages in thread
From: Evan Green @ 2019-01-23 22:11 UTC (permalink / raw)
  To: Andy Gross, Rob Herring, Kishon Vijay Abraham I
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Stephen Boyd,
	Vivek Gautam, Evan Green, devicetree, Mark Rutland, linux-kernel

Add a required reset to the SDM845 UFS phy to express the PHY reset
bit inside the UFS controller register space. Before this change, this
reset was not expressed in the DT, and the driver utilized two different
callbacks (phy_init and phy_poweron) to implement a two-phase
initialization procedure that involved deasserting this reset between
init and poweron. This abused the two callbacks and diluted their
purpose.

That scheme does not work as regulators cannot be turned off in
phy_poweroff because they were turned on in init, rather than poweron.
The net result is that regulators are left on in suspend that shouldn't
be.

This new scheme gives the UFS reset to the PHY, so that it can fully
initialize itself in a single callback. We can then turn regulators on
during poweron and off during poweroff.

Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
I realize I'm not supposed to add a required property after the fact,
but given that the UFS DT nodes that would use this binding are not
yet upstream (and this would be the first), I was hoping to squeak by.

Changes in v2: None

 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index 4ff26dbf43106..49b8a5eed3cd1 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -56,7 +56,8 @@ Required properties:
 	   one for each entry in reset-names.
  - reset-names: "phy" for reset of phy block,
 		"common" for phy common block reset,
-		"cfg" for phy's ahb cfg block reset.
+		"cfg" for phy's ahb cfg block reset,
+		"ufsphy" for the PHY reset in the UFS controller.
 
 		For "qcom,ipq8074-qmp-pcie-phy" must contain:
 			"phy", "common".
@@ -70,7 +71,8 @@ Required properties:
 			"phy", "common".
 		For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
 			"phy", "common".
-		For "qcom,sdm845-qmp-ufs-phy": no resets are listed.
+		For "qcom,sdm845-qmp-ufs-phy": must contain:
+			"ufsphy".
 
  - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
  - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
-- 
2.18.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 3/9] dt-bindings: phy: qcom-ufs: Add resets property
  2019-01-23 22:11 [PATCH v2 0/9] phy: qcom-ufs: Enable regulators to be off in suspend Evan Green
  2019-01-23 22:11 ` [PATCH v2 1/9] dt-bindings: ufs: Add #reset-cells for Qualcomm controllers Evan Green
  2019-01-23 22:11 ` [PATCH v2 2/9] dt-bindings: phy-qcom-qmp: Add UFS PHY reset Evan Green
@ 2019-01-23 22:11 ` Evan Green
  2019-02-01 17:41   ` Stephen Boyd
  2019-01-23 22:11 ` [PATCH v2 4/9] arm64: dts: sdm845: Add UFS PHY reset Evan Green
                   ` (5 subsequent siblings)
  8 siblings, 1 reply; 20+ messages in thread
From: Evan Green @ 2019-01-23 22:11 UTC (permalink / raw)
  To: Andy Gross, Rob Herring, Kishon Vijay Abraham I
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Stephen Boyd,
	Vivek Gautam, Evan Green, devicetree, Mark Rutland, linux-kernel

Add a resets property to the PHY that represents the PHY reset
register in the UFS controller itself. This better describes the
complete specification of the PHY, and allows the PHY to perform
its initialization in a single function, rather than relying on
back-channel sequencing of initialization through the PHY framework.

Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---

Changes in v2:
- Added resets to example (Stephen).

 Documentation/devicetree/bindings/ufs/ufs-qcom.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
index 21d9a93db2e97..fd59f93e95562 100644
--- a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
+++ b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
@@ -29,6 +29,7 @@ Optional properties:
 - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
 - vddp-ref-clk-supply   : phandle to UFS device ref_clk pad power supply
 - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply
+- resets : specifies the PHY reset in the UFS controller
 
 Example:
 
@@ -51,9 +52,11 @@ Example:
 			<&clock_gcc clk_ufs_phy_ldo>,
 			<&clock_gcc clk_gcc_ufs_tx_cfg_clk>,
 			<&clock_gcc clk_gcc_ufs_rx_cfg_clk>;
+		resets = <&ufshc 0>;
 	};
 
-	ufshc@fc598000 {
+	ufshc: ufshc@fc598000 {
+		#reset-cells = <1>;
 		...
 		phys = <&ufsphy1>;
 		phy-names = "ufsphy";
-- 
2.18.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 4/9] arm64: dts: sdm845: Add UFS PHY reset
  2019-01-23 22:11 [PATCH v2 0/9] phy: qcom-ufs: Enable regulators to be off in suspend Evan Green
                   ` (2 preceding siblings ...)
  2019-01-23 22:11 ` [PATCH v2 3/9] dt-bindings: phy: qcom-ufs: Add resets property Evan Green
@ 2019-01-23 22:11 ` Evan Green
  2019-01-23 22:11 ` [PATCH v2 5/9] arm64: dts: msm8996: Add UFS PHY reset controller Evan Green
                   ` (4 subsequent siblings)
  8 siblings, 0 replies; 20+ messages in thread
From: Evan Green @ 2019-01-23 22:11 UTC (permalink / raw)
  To: Andy Gross, Rob Herring, Kishon Vijay Abraham I
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Stephen Boyd,
	Vivek Gautam, Evan Green, devicetree, linux-arm-msm,
	linux-kernel, David Brown, Mark Rutland

Wire up the reset controller in the Qcom UFS controller for the PHY.
This will be used to toggle PHY reset during initialization of the PHY.

Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
This commit is based atop the series at [1]. Patches 1 and 2 of that
series have landed, but 3, 4, and 5 are still outstanding.

[1] https://lore.kernel.org/lkml/20181210192826.241350-1-evgreen@chromium.org/

Changes in v2: None

 arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index b29332b265d9e..029ab66405cf4 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -990,6 +990,7 @@
 			phy-names = "ufsphy";
 			lanes-per-direction = <2>;
 			power-domains = <&gcc UFS_PHY_GDSC>;
+			#reset-cells = <1>;
 
 			clock-names =
 				"core_clk",
@@ -1033,6 +1034,8 @@
 			clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
 				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
 
+			resets = <&ufs_mem_hc 0>;
+			reset-names = "ufsphy";
 			status = "disabled";
 
 			ufs_mem_phy_lanes: lanes@1d87400 {
-- 
2.18.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 5/9] arm64: dts: msm8996: Add UFS PHY reset controller
  2019-01-23 22:11 [PATCH v2 0/9] phy: qcom-ufs: Enable regulators to be off in suspend Evan Green
                   ` (3 preceding siblings ...)
  2019-01-23 22:11 ` [PATCH v2 4/9] arm64: dts: sdm845: Add UFS PHY reset Evan Green
@ 2019-01-23 22:11 ` Evan Green
  2019-01-23 22:11 ` [PATCH v2 6/9] scsi: ufs: qcom: Expose the reset controller for PHY Evan Green
                   ` (3 subsequent siblings)
  8 siblings, 0 replies; 20+ messages in thread
From: Evan Green @ 2019-01-23 22:11 UTC (permalink / raw)
  To: Andy Gross, Rob Herring, Kishon Vijay Abraham I
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Stephen Boyd,
	Vivek Gautam, Evan Green, devicetree, linux-arm-msm,
	linux-kernel, David Brown, Mark Rutland

Add the reset controller for the UFS controller, and wire it up
so that the UFS PHY can initialize itself without relying on
implicit sequencing between the two drivers.

Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---

Changes in v2: None

 arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 99b7495455a62..179f1988d45c5 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -663,10 +663,11 @@
 			clock-names = "ref_clk_src", "ref_clk";
 			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
 				 <&gcc GCC_UFS_CLKREF_CLK>;
+			resets = <&ufshc 0>;
 			status = "disabled";
 		};
 
-		ufshc@624000 {
+		ufshc: ufshc@624000 {
 			compatible = "qcom,ufshc";
 			reg = <0x624000 0x2500>;
 			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
@@ -722,6 +723,7 @@
 				<0 0>;
 
 			lanes-per-direction = <1>;
+			#reset-cells = <1>;
 			status = "disabled";
 
 			ufs_variant {
-- 
2.18.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 6/9] scsi: ufs: qcom: Expose the reset controller for PHY
  2019-01-23 22:11 [PATCH v2 0/9] phy: qcom-ufs: Enable regulators to be off in suspend Evan Green
                   ` (4 preceding siblings ...)
  2019-01-23 22:11 ` [PATCH v2 5/9] arm64: dts: msm8996: Add UFS PHY reset controller Evan Green
@ 2019-01-23 22:11 ` Evan Green
  2019-02-01 17:56   ` Stephen Boyd
  2019-01-23 22:11 ` [PATCH v2 7/9] phy: qcom-qmp: Utilize UFS reset controller Evan Green
                   ` (2 subsequent siblings)
  8 siblings, 1 reply; 20+ messages in thread
From: Evan Green @ 2019-01-23 22:11 UTC (permalink / raw)
  To: Andy Gross, Rob Herring, Kishon Vijay Abraham I
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Stephen Boyd,
	Vivek Gautam, Evan Green, James E.J. Bottomley,
	Vinayak Holikatti, Martin K. Petersen, linux-scsi, linux-kernel

Expose a reset controller that the phy can use to perform its
initialization in a single callback.

Also, change the use of the phy functions from ufs-qcom such that
phy_poweron actually fires up the phy, and phy_poweroff actually
powers it down.

Signed-off-by: Evan Green <evgreen@chromium.org>

---
Note: This change depends on the remaining changes in this series,
since UFS PHY reset now needs to be done by the PHY driver.

Changes in v2:
- Remove include of reset.h (Stephen)
- Fix error print of phy_power_on (Stephen)
- Comment for reset controller warnings on id != 0 (Stephen)
- Add static to ufs_qcom_reset_ops (Stephen).

 drivers/scsi/ufs/Kconfig    |   1 +
 drivers/scsi/ufs/ufs-qcom.c | 111 ++++++++++++++++++++++--------------
 drivers/scsi/ufs/ufs-qcom.h |   4 ++
 3 files changed, 72 insertions(+), 44 deletions(-)

diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
index 2ddbb26d9c265..63c5c4115981f 100644
--- a/drivers/scsi/ufs/Kconfig
+++ b/drivers/scsi/ufs/Kconfig
@@ -100,6 +100,7 @@ config SCSI_UFS_QCOM
 	tristate "QCOM specific hooks to UFS controller platform driver"
 	depends on SCSI_UFSHCD_PLATFORM && ARCH_QCOM
 	select PHY_QCOM_UFS
+	select RESET_CONTROLLER
 	help
 	  This selects the QCOM specific additions to UFSHCD platform driver.
 	  UFS host on QCOM needs some vendor specific configuration before
diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
index 3aeadb14aae1e..277ed6ad71c9b 100644
--- a/drivers/scsi/ufs/ufs-qcom.c
+++ b/drivers/scsi/ufs/ufs-qcom.c
@@ -49,6 +49,11 @@ static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
 						       u32 clk_cycles);
 
+static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
+{
+	return container_of(rcd, struct ufs_qcom_host, rcdev);
+}
+
 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
 				       const char *prefix, void *priv)
 {
@@ -255,11 +260,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
 	if (is_rate_B)
 		phy_set_mode(phy, PHY_MODE_UFS_HS_B);
 
-	/* Assert PHY reset and apply PHY calibration values */
-	ufs_qcom_assert_reset(hba);
-	/* provide 1ms delay to let the reset pulse propagate */
-	usleep_range(1000, 1100);
-
 	/* phy initialization - calibrate the phy */
 	ret = phy_init(phy);
 	if (ret) {
@@ -268,15 +268,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
 		goto out;
 	}
 
-	/* De-assert PHY reset and start serdes */
-	ufs_qcom_deassert_reset(hba);
-
-	/*
-	 * after reset deassertion, phy will need all ref clocks,
-	 * voltage, current to settle down before starting serdes.
-	 */
-	usleep_range(1000, 1100);
-
 	/* power on phy - start serdes and phy's power and clocks */
 	ret = phy_power_on(phy);
 	if (ret) {
@@ -290,7 +281,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
 	return 0;
 
 out_disable_phy:
-	ufs_qcom_assert_reset(hba);
 	phy_exit(phy);
 out:
 	return ret;
@@ -554,21 +544,10 @@ static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 		ufs_qcom_disable_lane_clks(host);
 		phy_power_off(phy);
 
-		/* Assert PHY soft reset */
-		ufs_qcom_assert_reset(hba);
-		goto out;
-	}
-
-	/*
-	 * If UniPro link is not active, PHY ref_clk, main PHY analog power
-	 * rail and low noise analog power rail for PLL can be switched off.
-	 */
-	if (!ufs_qcom_is_link_active(hba)) {
+	} else if (!ufs_qcom_is_link_active(hba)) {
 		ufs_qcom_disable_lane_clks(host);
-		phy_power_off(phy);
 	}
 
-out:
 	return ret;
 }
 
@@ -578,21 +557,26 @@ static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 	struct phy *phy = host->generic_phy;
 	int err;
 
-	err = phy_power_on(phy);
-	if (err) {
-		dev_err(hba->dev, "%s: failed enabling regs, err = %d\n",
-			__func__, err);
-		goto out;
-	}
+	if (ufs_qcom_is_link_off(hba)) {
+		err = phy_power_on(phy);
+		if (err) {
+			dev_err(hba->dev, "%s: failed PHY power on: %d\n",
+				__func__, err);
+			return err;
+		}
 
-	err = ufs_qcom_enable_lane_clks(host);
-	if (err)
-		goto out;
+		err = ufs_qcom_enable_lane_clks(host);
+		if (err)
+			return err;
 
-	hba->is_sys_suspended = false;
+	} else if (!ufs_qcom_is_link_active(hba)) {
+		err = ufs_qcom_enable_lane_clks(host);
+		if (err)
+			return err;
+	}
 
-out:
-	return err;
+	hba->is_sys_suspended = false;
+	return 0;
 }
 
 struct ufs_qcom_dev_params {
@@ -1118,8 +1102,6 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
 		return 0;
 
 	if (on && (status == POST_CHANGE)) {
-		phy_power_on(host->generic_phy);
-
 		/* enable the device ref clock for HS mode*/
 		if (ufshcd_is_hs_mode(&hba->pwr_info))
 			ufs_qcom_dev_ref_clk_ctrl(host, true);
@@ -1131,9 +1113,6 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
 		if (!ufs_qcom_is_link_active(hba)) {
 			/* disable device ref_clk */
 			ufs_qcom_dev_ref_clk_ctrl(host, false);
-
-			/* powering off PHY during aggressive clk gating */
-			phy_power_off(host->generic_phy);
 		}
 
 		vote = host->bus_vote.min_bw_vote;
@@ -1147,6 +1126,41 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
 	return err;
 }
 
+static int
+ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
+
+	/* Currently this code only knows about a single reset. */
+	WARN_ON(id);
+	ufs_qcom_assert_reset(host->hba);
+	/* provide 1ms delay to let the reset pulse propagate */
+	usleep_range(1000, 1100);
+	return 0;
+}
+
+static int
+ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
+
+	/* Currently this code only knows about a single reset. */
+	WARN_ON(id);
+	ufs_qcom_deassert_reset(host->hba);
+
+	/*
+	 * after reset deassertion, phy will need all ref clocks,
+	 * voltage, current to settle down before starting serdes.
+	 */
+	usleep_range(1000, 1100);
+	return 0;
+}
+
+const static struct reset_control_ops ufs_qcom_reset_ops = {
+	.assert = ufs_qcom_reset_assert,
+	.deassert = ufs_qcom_reset_deassert,
+};
+
 #define	ANDROID_BOOT_DEV_MAX	30
 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
 
@@ -1191,6 +1205,15 @@ static int ufs_qcom_init(struct ufs_hba *hba)
 	host->hba = hba;
 	ufshcd_set_variant(hba, host);
 
+	/* Fire up the reset controller. Failure here is non-fatal. */
+	host->rcdev.of_node = dev->of_node;
+	host->rcdev.ops = &ufs_qcom_reset_ops;
+	host->rcdev.owner = dev->driver->owner;
+	host->rcdev.nr_resets = 1;
+	err = devm_reset_controller_register(dev, &host->rcdev);
+	if (err)
+		dev_warn(dev, "Failed to register reset controller\n");
+
 	/*
 	 * voting/devoting device ref_clk source is time consuming hence
 	 * skip devoting it during aggressive clock gating. This clock
diff --git a/drivers/scsi/ufs/ufs-qcom.h b/drivers/scsi/ufs/ufs-qcom.h
index c114826316eb0..68a8801857529 100644
--- a/drivers/scsi/ufs/ufs-qcom.h
+++ b/drivers/scsi/ufs/ufs-qcom.h
@@ -14,6 +14,8 @@
 #ifndef UFS_QCOM_H_
 #define UFS_QCOM_H_
 
+#include <linux/reset-controller.h>
+
 #define MAX_UFS_QCOM_HOSTS	1
 #define MAX_U32                 (~(u32)0)
 #define MPHY_TX_FSM_STATE       0x41
@@ -237,6 +239,8 @@ struct ufs_qcom_host {
 	/* Bitmask for enabling debug prints */
 	u32 dbg_print_en;
 	struct ufs_qcom_testbus testbus;
+
+	struct reset_controller_dev rcdev;
 };
 
 static inline u32
-- 
2.18.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 7/9] phy: qcom-qmp: Utilize UFS reset controller
  2019-01-23 22:11 [PATCH v2 0/9] phy: qcom-ufs: Enable regulators to be off in suspend Evan Green
                   ` (5 preceding siblings ...)
  2019-01-23 22:11 ` [PATCH v2 6/9] scsi: ufs: qcom: Expose the reset controller for PHY Evan Green
@ 2019-01-23 22:11 ` Evan Green
  2019-02-01 18:00   ` Stephen Boyd
  2019-01-23 22:11 ` [PATCH v2 8/9] phy: qcom-qmp: Move UFS phy to phy_poweron/off Evan Green
  2019-01-23 22:11 ` [PATCH v2 9/9] phy: qcom-ufs: Refactor all init steps into phy_poweron Evan Green
  8 siblings, 1 reply; 20+ messages in thread
From: Evan Green @ 2019-01-23 22:11 UTC (permalink / raw)
  To: Andy Gross, Rob Herring, Kishon Vijay Abraham I
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Stephen Boyd,
	Vivek Gautam, Evan Green, Jeffrey Hugo, linux-kernel,
	Manu Gautam

Request the newly minted reset controller from the Qualcomm UFS
controller, and use it to toggle the PHY reset line from within
the PHY. This will allow us to merge the two phases of UFS PHY
initialization.

Signed-off-by: Evan Green <evgreen@chromium.org>

---
Note: this change is dependent on the previous changes, including
the DT changes, in order to expose the reset controller from UFS.

Changes in v2:
- Use devm_* to get the reset (Stephen)
- Clear ufs_reset on error getting it
- Remove needless error print (Stephen)

 drivers/phy/qualcomm/phy-qcom-qmp.c | 44 +++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index daf751500232f..721af5706fbb1 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -849,6 +849,9 @@ struct qmp_phy_cfg {
 
 	/* true, if PCS block has no separate SW_RESET register */
 	bool no_pcs_sw_reset;
+
+	/* true if the PHY has a UFS reset control to toggle */
+	bool has_ufsphy_reset;
 };
 
 /**
@@ -897,6 +900,7 @@ struct qmp_phy {
  * @init_count: phy common block initialization count
  * @phy_initialized: indicate if PHY has been initialized
  * @mode: current PHY mode
+ * @ufs_reset: optional UFS PHY reset handle
  */
 struct qcom_qmp {
 	struct device *dev;
@@ -914,6 +918,8 @@ struct qcom_qmp {
 	int init_count;
 	bool phy_initialized;
 	enum phy_mode mode;
+
+	struct reset_control *ufs_reset;
 };
 
 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
@@ -1144,6 +1150,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
 
 	.is_dual_lane_phy	= true,
 	.no_pcs_sw_reset	= true,
+
+	.has_ufsphy_reset	= true,
 };
 
 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
@@ -1314,6 +1322,9 @@ static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
 		return 0;
 	}
 
+	if (qmp->ufs_reset)
+		reset_control_assert(qmp->ufs_reset);
+
 	if (cfg->has_phy_com_ctrl) {
 		qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
 			     SERDES_START | PCS_START);
@@ -1351,6 +1362,33 @@ static int qcom_qmp_phy_init(struct phy *phy)
 
 	dev_vdbg(qmp->dev, "Initializing QMP phy\n");
 
+	if (cfg->has_ufsphy_reset) {
+		/*
+		 * Get UFS reset, which is delayed until now to avoid a
+		 * circular dependency where UFS needs its PHY, but the PHY
+		 * needs this UFS reset.
+		 */
+		if (!qmp->ufs_reset) {
+			qmp->ufs_reset =
+				devm_reset_control_get_exclusive(qmp->dev,
+								 "ufsphy");
+
+			if (IS_ERR(qmp->ufs_reset)) {
+				dev_err(qmp->dev,
+					"failed to get UFS reset: %d\n",
+					PTR_ERR(qmp->ufs_reset));
+
+				ret = PTR_ERR(qmp->ufs_reset);
+				qmp->ufs_reset = NULL;
+				return ret;
+			}
+		}
+
+		ret = reset_control_assert(qmp->ufs_reset);
+		if (ret)
+			goto err_lane_rst;
+	}
+
 	ret = qcom_qmp_phy_com_init(qphy);
 	if (ret)
 		return ret;
@@ -1384,6 +1422,12 @@ static int qcom_qmp_phy_init(struct phy *phy)
 
 	qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
 
+	if (qmp->ufs_reset) {
+		ret = reset_control_deassert(qmp->ufs_reset);
+		if (ret)
+			goto err_lane_rst;
+	}
+
 	/*
 	 * UFS PHY requires the deassert of software reset before serdes start.
 	 * For UFS PHYs that do not have software reset control bits, defer
-- 
2.18.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 8/9] phy: qcom-qmp: Move UFS phy to phy_poweron/off
  2019-01-23 22:11 [PATCH v2 0/9] phy: qcom-ufs: Enable regulators to be off in suspend Evan Green
                   ` (6 preceding siblings ...)
  2019-01-23 22:11 ` [PATCH v2 7/9] phy: qcom-qmp: Utilize UFS reset controller Evan Green
@ 2019-01-23 22:11 ` Evan Green
  2019-01-23 22:11 ` [PATCH v2 9/9] phy: qcom-ufs: Refactor all init steps into phy_poweron Evan Green
  8 siblings, 0 replies; 20+ messages in thread
From: Evan Green @ 2019-01-23 22:11 UTC (permalink / raw)
  To: Andy Gross, Rob Herring, Kishon Vijay Abraham I
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Stephen Boyd,
	Vivek Gautam, Evan Green, Jeffrey Hugo, linux-kernel,
	Manu Gautam

For UFS, move the actual firing up of the PHY to phy_poweron and
phy_poweroff callbacks, rather than init/exit. UFS calls
phy_poweroff during suspend, so now all clocks and regulators for
the phy can be powered down during suspend.

Signed-off-by: Evan Green <evgreen@chromium.org>

---

Changes in v2:
- Removed whitespace changes (Stephen)

 drivers/phy/qualcomm/phy-qcom-qmp.c | 80 +++++++++--------------------
 1 file changed, 23 insertions(+), 57 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 721af5706fbb1..fa32b2837e708 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -1346,8 +1346,7 @@ static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
 	return 0;
 }
 
-/* PHY Initialization */
-static int qcom_qmp_phy_init(struct phy *phy)
+static int qcom_qmp_phy_enable(struct phy *phy)
 {
 	struct qmp_phy *qphy = phy_get_drvdata(phy);
 	struct qcom_qmp *qmp = qphy->qmp;
@@ -1428,14 +1427,6 @@ static int qcom_qmp_phy_init(struct phy *phy)
 			goto err_lane_rst;
 	}
 
-	/*
-	 * UFS PHY requires the deassert of software reset before serdes start.
-	 * For UFS PHYs that do not have software reset control bits, defer
-	 * starting serdes until the power on callback.
-	 */
-	if ((cfg->type == PHY_TYPE_UFS) && cfg->no_pcs_sw_reset)
-		goto out;
-
 	/*
 	 * Pull out PHY from POWER DOWN state.
 	 * This is active low enable signal to power-down PHY.
@@ -1447,7 +1438,9 @@ static int qcom_qmp_phy_init(struct phy *phy)
 		usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
 
 	/* Pull PHY out of reset state */
-	qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
+	if (!cfg->no_pcs_sw_reset)
+		qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
+
 	if (cfg->has_phy_dp_com_ctrl)
 		qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
 
@@ -1464,11 +1457,12 @@ static int qcom_qmp_phy_init(struct phy *phy)
 		goto err_pcs_ready;
 	}
 	qmp->phy_initialized = true;
-
-out:
-	return ret;
+	return 0;
 
 err_pcs_ready:
+	if (qmp->ufs_reset)
+		reset_control_assert(qmp->ufs_reset);
+
 	clk_disable_unprepare(qphy->pipe_clk);
 err_clk_enable:
 	if (cfg->has_lane_rst)
@@ -1479,7 +1473,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
 	return ret;
 }
 
-static int qcom_qmp_phy_exit(struct phy *phy)
+static int qcom_qmp_phy_disable(struct phy *phy)
 {
 	struct qmp_phy *qphy = phy_get_drvdata(phy);
 	struct qcom_qmp *qmp = qphy->qmp;
@@ -1507,44 +1501,6 @@ static int qcom_qmp_phy_exit(struct phy *phy)
 	return 0;
 }
 
-static int qcom_qmp_phy_poweron(struct phy *phy)
-{
-	struct qmp_phy *qphy = phy_get_drvdata(phy);
-	struct qcom_qmp *qmp = qphy->qmp;
-	const struct qmp_phy_cfg *cfg = qmp->cfg;
-	void __iomem *pcs = qphy->pcs;
-	void __iomem *status;
-	unsigned int mask, val;
-	int ret = 0;
-
-	if (cfg->type != PHY_TYPE_UFS)
-		return 0;
-
-	/*
-	 * For UFS PHY that has not software reset control, serdes start
-	 * should only happen when UFS driver explicitly calls phy_power_on
-	 * after it deasserts software reset.
-	 */
-	if (cfg->no_pcs_sw_reset && !qmp->phy_initialized &&
-	    (qmp->init_count != 0)) {
-		/* start SerDes and Phy-Coding-Sublayer */
-		qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
-		status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-		mask = cfg->mask_pcs_ready;
-
-		ret = readl_poll_timeout(status, val, !(val & mask), 1,
-					 PHY_INIT_COMPLETE_TIMEOUT);
-		if (ret) {
-			dev_err(qmp->dev, "phy initialization timed-out\n");
-			return ret;
-		}
-		qmp->phy_initialized = true;
-	}
-
-	return ret;
-}
-
 static int qcom_qmp_phy_set_mode(struct phy *phy,
 				 enum phy_mode mode, int submode)
 {
@@ -1794,9 +1750,15 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
 }
 
 static const struct phy_ops qcom_qmp_phy_gen_ops = {
-	.init		= qcom_qmp_phy_init,
-	.exit		= qcom_qmp_phy_exit,
-	.power_on	= qcom_qmp_phy_poweron,
+	.init		= qcom_qmp_phy_enable,
+	.exit		= qcom_qmp_phy_disable,
+	.set_mode	= qcom_qmp_phy_set_mode,
+	.owner		= THIS_MODULE,
+};
+
+static const struct phy_ops qcom_qmp_ufs_ops = {
+	.power_on	= qcom_qmp_phy_enable,
+	.power_off	= qcom_qmp_phy_disable,
 	.set_mode	= qcom_qmp_phy_set_mode,
 	.owner		= THIS_MODULE,
 };
@@ -1807,6 +1769,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
 	struct qcom_qmp *qmp = dev_get_drvdata(dev);
 	struct phy *generic_phy;
 	struct qmp_phy *qphy;
+	const struct phy_ops *ops = &qcom_qmp_phy_gen_ops;
 	char prop_name[MAX_PROP_NAME];
 	int ret;
 
@@ -1893,7 +1856,10 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
 		}
 	}
 
-	generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_gen_ops);
+	if (qmp->cfg->type == PHY_TYPE_UFS)
+		ops = &qcom_qmp_ufs_ops;
+
+	generic_phy = devm_phy_create(dev, np, ops);
 	if (IS_ERR(generic_phy)) {
 		ret = PTR_ERR(generic_phy);
 		dev_err(dev, "failed to create qphy %d\n", ret);
-- 
2.18.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 9/9] phy: qcom-ufs: Refactor all init steps into phy_poweron
  2019-01-23 22:11 [PATCH v2 0/9] phy: qcom-ufs: Enable regulators to be off in suspend Evan Green
                   ` (7 preceding siblings ...)
  2019-01-23 22:11 ` [PATCH v2 8/9] phy: qcom-qmp: Move UFS phy to phy_poweron/off Evan Green
@ 2019-01-23 22:11 ` Evan Green
  2019-02-01 18:43   ` Stephen Boyd
  8 siblings, 1 reply; 20+ messages in thread
From: Evan Green @ 2019-01-23 22:11 UTC (permalink / raw)
  To: Andy Gross, Rob Herring, Kishon Vijay Abraham I
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Stephen Boyd,
	Vivek Gautam, Evan Green, Bjorn Andersson, Arnd Bergmann,
	Grygorii Strashko, Marc Gonzalez, linux-kernel,
	Martin K. Petersen

The phy code was using implicit sequencing between the PHY driver
and the UFS driver to implement certain hardware requirements.
Specifically, the PHY reset register in the UFS controller needs
to be deasserted before serdes start occurs in the PHY.

Before this change, the code was doing this by utilizing the two
phy callbacks, phy_init and phy_poweron, as "init step 1" and
"init step 2", where the UFS driver would deassert reset between
these two steps.

This makes it challenging to power off the regulators in suspend,
as regulators are initialized in init, not in poweron, but only
poweroff is called during suspend, not exit.

Consolidate the initialization code into phy_poweron, and utilize
the reset controller exported from the UFS driver to explicitly
perform all the steps needed to initialize the PHY.

Signed-off-by: Evan Green <evgreen@chromium.org>
---

Changes in v2:
- Use devm_ to get the reset (Stephen)

 drivers/phy/qualcomm/phy-qcom-ufs-i.h        |  5 +-
 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c | 25 +--------
 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c | 25 +--------
 drivers/phy/qualcomm/phy-qcom-ufs.c          | 57 +++++++++++++++-----
 4 files changed, 49 insertions(+), 63 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-i.h b/drivers/phy/qualcomm/phy-qcom-ufs-i.h
index f798fb64de94e..109ddd67be829 100644
--- a/drivers/phy/qualcomm/phy-qcom-ufs-i.h
+++ b/drivers/phy/qualcomm/phy-qcom-ufs-i.h
@@ -19,6 +19,7 @@
 #include <linux/clk.h>
 #include <linux/phy/phy.h>
 #include <linux/regulator/consumer.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -96,11 +97,10 @@ struct ufs_qcom_phy {
 	char name[UFS_QCOM_PHY_NAME_LEN];
 	struct ufs_qcom_phy_calibration *cached_regs;
 	int cached_regs_table_size;
-	bool is_powered_on;
-	bool is_started;
 	struct ufs_qcom_phy_specific_ops *phy_spec_ops;
 
 	enum phy_mode mode;
+	struct reset_control *ufs_reset;
 };
 
 /**
@@ -115,6 +115,7 @@ struct ufs_qcom_phy {
  * and writes to QSERDES_RX_SIGDET_CNTRL attribute
  */
 struct ufs_qcom_phy_specific_ops {
+	int (*calibrate)(struct ufs_qcom_phy *ufs_qcom_phy, bool is_rate_B);
 	void (*start_serdes)(struct ufs_qcom_phy *phy);
 	int (*is_physical_coding_sublayer_ready)(struct ufs_qcom_phy *phy);
 	void (*set_tx_lane_enable)(struct ufs_qcom_phy *phy, u32 val);
diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c
index 1e0d4f2046a45..4815546f228cd 100644
--- a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c
+++ b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c
@@ -42,28 +42,6 @@ void ufs_qcom_phy_qmp_14nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
 		UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
 }
 
-static int ufs_qcom_phy_qmp_14nm_init(struct phy *generic_phy)
-{
-	struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
-	bool is_rate_B = false;
-	int ret;
-
-	if (phy_common->mode == PHY_MODE_UFS_HS_B)
-		is_rate_B = true;
-
-	ret = ufs_qcom_phy_qmp_14nm_phy_calibrate(phy_common, is_rate_B);
-	if (!ret)
-		/* phy calibrated, but yet to be started */
-		phy_common->is_started = false;
-
-	return ret;
-}
-
-static int ufs_qcom_phy_qmp_14nm_exit(struct phy *generic_phy)
-{
-	return 0;
-}
-
 static
 int ufs_qcom_phy_qmp_14nm_set_mode(struct phy *generic_phy,
 				   enum phy_mode mode, int submode)
@@ -124,8 +102,6 @@ static int ufs_qcom_phy_qmp_14nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
 }
 
 static const struct phy_ops ufs_qcom_phy_qmp_14nm_phy_ops = {
-	.init		= ufs_qcom_phy_qmp_14nm_init,
-	.exit		= ufs_qcom_phy_qmp_14nm_exit,
 	.power_on	= ufs_qcom_phy_power_on,
 	.power_off	= ufs_qcom_phy_power_off,
 	.set_mode	= ufs_qcom_phy_qmp_14nm_set_mode,
@@ -133,6 +109,7 @@ static const struct phy_ops ufs_qcom_phy_qmp_14nm_phy_ops = {
 };
 
 static struct ufs_qcom_phy_specific_ops phy_14nm_ops = {
+	.calibrate		= ufs_qcom_phy_qmp_14nm_phy_calibrate,
 	.start_serdes		= ufs_qcom_phy_qmp_14nm_start_serdes,
 	.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_14nm_is_pcs_ready,
 	.set_tx_lane_enable	= ufs_qcom_phy_qmp_14nm_set_tx_lane_enable,
diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c
index aef40f7a41d49..f1cf819e12eae 100644
--- a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c
+++ b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c
@@ -61,28 +61,6 @@ void ufs_qcom_phy_qmp_20nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
 		UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
 }
 
-static int ufs_qcom_phy_qmp_20nm_init(struct phy *generic_phy)
-{
-	struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
-	bool is_rate_B = false;
-	int ret;
-
-	if (phy_common->mode == PHY_MODE_UFS_HS_B)
-		is_rate_B = true;
-
-	ret = ufs_qcom_phy_qmp_20nm_phy_calibrate(phy_common, is_rate_B);
-	if (!ret)
-		/* phy calibrated, but yet to be started */
-		phy_common->is_started = false;
-
-	return ret;
-}
-
-static int ufs_qcom_phy_qmp_20nm_exit(struct phy *generic_phy)
-{
-	return 0;
-}
-
 static
 int ufs_qcom_phy_qmp_20nm_set_mode(struct phy *generic_phy,
 				   enum phy_mode mode, int submode)
@@ -182,8 +160,6 @@ static int ufs_qcom_phy_qmp_20nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
 }
 
 static const struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {
-	.init		= ufs_qcom_phy_qmp_20nm_init,
-	.exit		= ufs_qcom_phy_qmp_20nm_exit,
 	.power_on	= ufs_qcom_phy_power_on,
 	.power_off	= ufs_qcom_phy_power_off,
 	.set_mode	= ufs_qcom_phy_qmp_20nm_set_mode,
@@ -191,6 +167,7 @@ static const struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {
 };
 
 static struct ufs_qcom_phy_specific_ops phy_20nm_ops = {
+	.calibrate		= ufs_qcom_phy_qmp_20nm_phy_calibrate,
 	.start_serdes		= ufs_qcom_phy_qmp_20nm_start_serdes,
 	.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_20nm_is_pcs_ready,
 	.set_tx_lane_enable	= ufs_qcom_phy_qmp_20nm_set_tx_lane_enable,
diff --git a/drivers/phy/qualcomm/phy-qcom-ufs.c b/drivers/phy/qualcomm/phy-qcom-ufs.c
index f2979ccad00a3..8860ced486f35 100644
--- a/drivers/phy/qualcomm/phy-qcom-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-ufs.c
@@ -147,6 +147,21 @@ struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
 }
 EXPORT_SYMBOL_GPL(ufs_qcom_phy_generic_probe);
 
+static int ufs_qcom_phy_get_reset(struct ufs_qcom_phy *phy_common)
+{
+	struct reset_control *reset;
+
+	if (phy_common->ufs_reset)
+		return 0;
+
+	reset = devm_reset_control_get_exclusive_by_index(phy_common->dev, 0);
+	if (IS_ERR(reset))
+		return PTR_ERR(reset);
+
+	phy_common->ufs_reset = reset;
+	return 0;
+}
+
 static int __ufs_qcom_phy_clk_get(struct device *dev,
 			 const char *name, struct clk **clk_out, bool err_print)
 {
@@ -528,23 +543,42 @@ int ufs_qcom_phy_power_on(struct phy *generic_phy)
 {
 	struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
 	struct device *dev = phy_common->dev;
+	bool is_rate_B = false;
 	int err;
 
-	if (phy_common->is_powered_on)
-		return 0;
+	err = ufs_qcom_phy_get_reset(phy_common);
+	if (err)
+		return err;
 
-	if (!phy_common->is_started) {
-		err = ufs_qcom_phy_start_serdes(phy_common);
+	if (phy_common->ufs_reset) {
+		err = reset_control_assert(phy_common->ufs_reset);
 		if (err)
 			return err;
+	}
 
-		err = ufs_qcom_phy_is_pcs_ready(phy_common);
-		if (err)
-			return err;
+	if (phy_common->mode == PHY_MODE_UFS_HS_B)
+		is_rate_B = true;
 
-		phy_common->is_started = true;
+	err = phy_common->phy_spec_ops->calibrate(phy_common, is_rate_B);
+	if (err)
+		return err;
+
+	if (phy_common->ufs_reset) {
+		err = reset_control_deassert(phy_common->ufs_reset);
+		if (err) {
+			dev_err(dev, "Failed to assert UFS PHY reset");
+			return err;
+		}
 	}
 
+	err = ufs_qcom_phy_start_serdes(phy_common);
+	if (err)
+		return err;
+
+	err = ufs_qcom_phy_is_pcs_ready(phy_common);
+	if (err)
+		return err;
+
 	err = ufs_qcom_phy_enable_vreg(dev, &phy_common->vdda_phy);
 	if (err) {
 		dev_err(dev, "%s enable vdda_phy failed, err=%d\n",
@@ -587,7 +621,6 @@ int ufs_qcom_phy_power_on(struct phy *generic_phy)
 		}
 	}
 
-	phy_common->is_powered_on = true;
 	goto out;
 
 out_disable_ref_clk:
@@ -607,9 +640,6 @@ int ufs_qcom_phy_power_off(struct phy *generic_phy)
 {
 	struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
 
-	if (!phy_common->is_powered_on)
-		return 0;
-
 	phy_common->phy_spec_ops->power_control(phy_common, false);
 
 	if (phy_common->vddp_ref_clk.reg)
@@ -620,7 +650,8 @@ int ufs_qcom_phy_power_off(struct phy *generic_phy)
 
 	ufs_qcom_phy_disable_vreg(phy_common->dev, &phy_common->vdda_pll);
 	ufs_qcom_phy_disable_vreg(phy_common->dev, &phy_common->vdda_phy);
-	phy_common->is_powered_on = false;
+	if (phy_common->ufs_reset)
+		reset_control_assert(phy_common->ufs_reset);
 
 	return 0;
 }
-- 
2.18.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread

* Re: [PATCH v2 1/9] dt-bindings: ufs: Add #reset-cells for Qualcomm controllers
  2019-01-23 22:11 ` [PATCH v2 1/9] dt-bindings: ufs: Add #reset-cells for Qualcomm controllers Evan Green
@ 2019-01-30 18:56   ` Rob Herring
  2019-02-01 17:41   ` Stephen Boyd
  1 sibling, 0 replies; 20+ messages in thread
From: Rob Herring @ 2019-01-30 18:56 UTC (permalink / raw)
  To: Evan Green
  Cc: Andy Gross, Kishon Vijay Abraham I, Can Guo, Douglas Anderson,
	Asutosh Das, Stephen Boyd, Vivek Gautam, Evan Green, devicetree,
	liwei, linux-kernel, Subhash Jadavani, Martin K. Petersen,
	Mark Rutland

On Wed, 23 Jan 2019 14:11:29 -0800, Evan Green wrote:
> Enable Qualcomm UFS controllers to expose the PHY reset via a reset
> controller.
> 
> Signed-off-by: Evan Green <evgreen@chromium.org>
> 
> ---
> Fixing up this aspect of it made me notice that this patch [1]
> hasn't landed yet. It really ought to.
> 
> [1] https://lore.kernel.org/lkml/20181012213926.253765-1-dianders@chromium.org/T/#u
> 
> Changes in v2: None
> 
>  Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | 3 +++
>  1 file changed, 3 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v2 1/9] dt-bindings: ufs: Add #reset-cells for Qualcomm controllers
  2019-01-23 22:11 ` [PATCH v2 1/9] dt-bindings: ufs: Add #reset-cells for Qualcomm controllers Evan Green
  2019-01-30 18:56   ` Rob Herring
@ 2019-02-01 17:41   ` Stephen Boyd
  1 sibling, 0 replies; 20+ messages in thread
From: Stephen Boyd @ 2019-02-01 17:41 UTC (permalink / raw)
  To: Andy Gross, Evan Green, Kishon Vijay Abraham I, Rob Herring
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Vivek Gautam, Evan Green,
	devicetree, liwei, linux-kernel, Subhash Jadavani,
	Martin K. Petersen, Mark Rutland

Quoting Evan Green (2019-01-23 14:11:29)
> Enable Qualcomm UFS controllers to expose the PHY reset via a reset
> controller.
> 
> Signed-off-by: Evan Green <evgreen@chromium.org>
> 
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v2 2/9] dt-bindings: phy-qcom-qmp: Add UFS PHY reset
  2019-01-23 22:11 ` [PATCH v2 2/9] dt-bindings: phy-qcom-qmp: Add UFS PHY reset Evan Green
@ 2019-02-01 17:41   ` Stephen Boyd
  0 siblings, 0 replies; 20+ messages in thread
From: Stephen Boyd @ 2019-02-01 17:41 UTC (permalink / raw)
  To: Andy Gross, Evan Green, Kishon Vijay Abraham I, Rob Herring
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Vivek Gautam, Evan Green,
	devicetree, Mark Rutland, linux-kernel

Quoting Evan Green (2019-01-23 14:11:30)
> Add a required reset to the SDM845 UFS phy to express the PHY reset
> bit inside the UFS controller register space. Before this change, this
> reset was not expressed in the DT, and the driver utilized two different
> callbacks (phy_init and phy_poweron) to implement a two-phase
> initialization procedure that involved deasserting this reset between
> init and poweron. This abused the two callbacks and diluted their
> purpose.
> 
> That scheme does not work as regulators cannot be turned off in
> phy_poweroff because they were turned on in init, rather than poweron.
> The net result is that regulators are left on in suspend that shouldn't
> be.
> 
> This new scheme gives the UFS reset to the PHY, so that it can fully
> initialize itself in a single callback. We can then turn regulators on
> during poweron and off during poweroff.
> 
> Signed-off-by: Evan Green <evgreen@chromium.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v2 3/9] dt-bindings: phy: qcom-ufs: Add resets property
  2019-01-23 22:11 ` [PATCH v2 3/9] dt-bindings: phy: qcom-ufs: Add resets property Evan Green
@ 2019-02-01 17:41   ` Stephen Boyd
  0 siblings, 0 replies; 20+ messages in thread
From: Stephen Boyd @ 2019-02-01 17:41 UTC (permalink / raw)
  To: Andy Gross, Evan Green, Kishon Vijay Abraham I, Rob Herring
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Vivek Gautam, Evan Green,
	devicetree, Mark Rutland, linux-kernel

Quoting Evan Green (2019-01-23 14:11:31)
> Add a resets property to the PHY that represents the PHY reset
> register in the UFS controller itself. This better describes the
> complete specification of the PHY, and allows the PHY to perform
> its initialization in a single function, rather than relying on
> back-channel sequencing of initialization through the PHY framework.
> 
> Signed-off-by: Evan Green <evgreen@chromium.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v2 6/9] scsi: ufs: qcom: Expose the reset controller for PHY
  2019-01-23 22:11 ` [PATCH v2 6/9] scsi: ufs: qcom: Expose the reset controller for PHY Evan Green
@ 2019-02-01 17:56   ` Stephen Boyd
  2019-02-05 17:59     ` Evan Green
  0 siblings, 1 reply; 20+ messages in thread
From: Stephen Boyd @ 2019-02-01 17:56 UTC (permalink / raw)
  To: Andy Gross, Evan Green, Kishon Vijay Abraham I, Rob Herring
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Vivek Gautam, Evan Green,
	James E.J. Bottomley, Vinayak Holikatti, Martin K. Petersen,
	linux-scsi, linux-kernel

Quoting Evan Green (2019-01-23 14:11:34)
> Expose a reset controller that the phy can use to perform its
> initialization in a single callback.
> 
> Also, change the use of the phy functions from ufs-qcom such that
> phy_poweron actually fires up the phy, and phy_poweroff actually
> powers it down.

This looks like two patches. One introduces a reset controller and the
other changes the phy functions somehow. Can this be split up and then
the commit text for the second half to change the phy functions can
explain a little more of the theory behind how it's OK to change the
code flow that way?

> 
> Signed-off-by: Evan Green <evgreen@chromium.org>
> 
> ---
> Note: This change depends on the remaining changes in this series,
> since UFS PHY reset now needs to be done by the PHY driver.

What does it depend on? Is there a bisection hole introduced here? An by
bisection hole I mean more than the problem that an older DT is used
with this new code.

> 
> Changes in v2:
> - Remove include of reset.h (Stephen)

Usually we include headers in both the C file and the header files that
use structs from header files. It wouldn't hurt to include
reset-controller.h in the ufs-qcom.c file. For one thing, it would help
a grep find reset controller drivers trim based on files ending in .c
instead of having to figure out which C file includes the .h file where
the reset-controller header is included.

> - Fix error print of phy_power_on (Stephen)
> - Comment for reset controller warnings on id != 0 (Stephen)
> - Add static to ufs_qcom_reset_ops (Stephen).
> 
>  drivers/scsi/ufs/Kconfig    |   1 +
>  drivers/scsi/ufs/ufs-qcom.c | 111 ++++++++++++++++++++++--------------
>  drivers/scsi/ufs/ufs-qcom.h |   4 ++
>  3 files changed, 72 insertions(+), 44 deletions(-)
> 
> diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
> index 3aeadb14aae1e..277ed6ad71c9b 100644
> --- a/drivers/scsi/ufs/ufs-qcom.c
> +++ b/drivers/scsi/ufs/ufs-qcom.c
> @@ -255,11 +260,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
>         if (is_rate_B)
>                 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
>  
> -       /* Assert PHY reset and apply PHY calibration values */
> -       ufs_qcom_assert_reset(hba);
> -       /* provide 1ms delay to let the reset pulse propagate */
> -       usleep_range(1000, 1100);
> -
>         /* phy initialization - calibrate the phy */
>         ret = phy_init(phy);
>         if (ret) {
> @@ -268,15 +268,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
>                 goto out;
>         }
>  
> -       /* De-assert PHY reset and start serdes */
> -       ufs_qcom_deassert_reset(hba);
> -
> -       /*
> -        * after reset deassertion, phy will need all ref clocks,
> -        * voltage, current to settle down before starting serdes.
> -        */
> -       usleep_range(1000, 1100);
> -
>         /* power on phy - start serdes and phy's power and clocks */
>         ret = phy_power_on(phy);
>         if (ret) {
> @@ -290,7 +281,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
>         return 0;
>  
>  out_disable_phy:
> -       ufs_qcom_assert_reset(hba);
>         phy_exit(phy);
>  out:
>         return ret;
> @@ -554,21 +544,10 @@ static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
>                 ufs_qcom_disable_lane_clks(host);
>                 phy_power_off(phy);
>  
> -               /* Assert PHY soft reset */
> -               ufs_qcom_assert_reset(hba);
> -               goto out;
> -       }
> -
> -       /*
> -        * If UniPro link is not active, PHY ref_clk, main PHY analog power
> -        * rail and low noise analog power rail for PLL can be switched off.
> -        */
> -       if (!ufs_qcom_is_link_active(hba)) {
> +       } else if (!ufs_qcom_is_link_active(hba)) {
>                 ufs_qcom_disable_lane_clks(host);
> -               phy_power_off(phy);
>         }
>  
> -out:
>         return ret;
>  }
>  
> @@ -578,21 +557,26 @@ static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
>         struct phy *phy = host->generic_phy;
>         int err;
>  
> -       err = phy_power_on(phy);
> -       if (err) {
> -               dev_err(hba->dev, "%s: failed enabling regs, err = %d\n",
> -                       __func__, err);
> -               goto out;
> -       }
> +       if (ufs_qcom_is_link_off(hba)) {
> +               err = phy_power_on(phy);
> +               if (err) {
> +                       dev_err(hba->dev, "%s: failed PHY power on: %d\n",
> +                               __func__, err);
> +                       return err;
> +               }
>  
> -       err = ufs_qcom_enable_lane_clks(host);
> -       if (err)
> -               goto out;
> +               err = ufs_qcom_enable_lane_clks(host);
> +               if (err)
> +                       return err;
>  
> -       hba->is_sys_suspended = false;
> +       } else if (!ufs_qcom_is_link_active(hba)) {
> +               err = ufs_qcom_enable_lane_clks(host);
> +               if (err)
> +                       return err;
> +       }
>  
> -out:
> -       return err;
> +       hba->is_sys_suspended = false;
> +       return 0;
>  }
>  
>  struct ufs_qcom_dev_params {
> @@ -1118,8 +1102,6 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
>                 return 0;
>  
>         if (on && (status == POST_CHANGE)) {
> -               phy_power_on(host->generic_phy);
> -
>                 /* enable the device ref clock for HS mode*/
>                 if (ufshcd_is_hs_mode(&hba->pwr_info))
>                         ufs_qcom_dev_ref_clk_ctrl(host, true);
> @@ -1131,9 +1113,6 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
>                 if (!ufs_qcom_is_link_active(hba)) {
>                         /* disable device ref_clk */
>                         ufs_qcom_dev_ref_clk_ctrl(host, false);
> -
> -                       /* powering off PHY during aggressive clk gating */
> -                       phy_power_off(host->generic_phy);
>                 }
>  
>                 vote = host->bus_vote.min_bw_vote;

All the above hunks should probably be another patch with a motivation
and explanation about what's going on in the commit text.

> @@ -1147,6 +1126,41 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
>         return err;
>  }
>  
> +static int
> +ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> +       struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
> +
> +       /* Currently this code only knows about a single reset. */

Ultra nitpick: Drop the full stop to be consistent with single line
comment style in this function?

> +       WARN_ON(id);
> +       ufs_qcom_assert_reset(host->hba);
> +       /* provide 1ms delay to let the reset pulse propagate */
> +       usleep_range(1000, 1100);
> +       return 0;
> +}
> +
> +static int
> +ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> +       struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
> +
> +       /* Currently this code only knows about a single reset. */

Well now it's different!

> +       WARN_ON(id);
> +       ufs_qcom_deassert_reset(host->hba);
> +
> +       /*
> +        * after reset deassertion, phy will need all ref clocks,
> +        * voltage, current to settle down before starting serdes.
> +        */
> +       usleep_range(1000, 1100);
> +       return 0;
> +}
> +
> +const static struct reset_control_ops ufs_qcom_reset_ops = {

const goes after static. Funny, there are some other grep hits for
'const static' in the kernel, but it's a small minority. Maybe those
should be fixed.

> +       .assert = ufs_qcom_reset_assert,
> +       .deassert = ufs_qcom_reset_deassert,
> +};
> +
>  #define        ANDROID_BOOT_DEV_MAX    30
>  static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
>  

Ooh Android!

> @@ -1191,6 +1205,15 @@ static int ufs_qcom_init(struct ufs_hba *hba)
>         host->hba = hba;
>         ufshcd_set_variant(hba, host);
>  
> +       /* Fire up the reset controller. Failure here is non-fatal. */
> +       host->rcdev.of_node = dev->of_node;
> +       host->rcdev.ops = &ufs_qcom_reset_ops;
> +       host->rcdev.owner = dev->driver->owner;
> +       host->rcdev.nr_resets = 1;
> +       err = devm_reset_controller_register(dev, &host->rcdev);
> +       if (err)
> +               dev_warn(dev, "Failed to register reset controller\n");

reset err to 0 because we don't care to fail here (it's just a warn, not
a dev_err)?

> +
>         /*
>          * voting/devoting device ref_clk source is time consuming hence
>          * skip devoting it during aggressive clock gating. This clock

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v2 7/9] phy: qcom-qmp: Utilize UFS reset controller
  2019-01-23 22:11 ` [PATCH v2 7/9] phy: qcom-qmp: Utilize UFS reset controller Evan Green
@ 2019-02-01 18:00   ` Stephen Boyd
  2019-02-05 18:00     ` Evan Green
  0 siblings, 1 reply; 20+ messages in thread
From: Stephen Boyd @ 2019-02-01 18:00 UTC (permalink / raw)
  To: Andy Gross, Evan Green, Kishon Vijay Abraham I, Rob Herring
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Vivek Gautam, Evan Green,
	Jeffrey Hugo, linux-kernel, Manu Gautam

Quoting Evan Green (2019-01-23 14:11:35)
> @@ -1144,6 +1150,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
>  
>         .is_dual_lane_phy       = true,
>         .no_pcs_sw_reset        = true,
> +
> +       .has_ufsphy_reset       = true,

Is this the same as .no_pcs_sw_reset implying that .has_ufsphy_reset? Or
it's possible to have no resets at all? I'd think there's a reset in the
phy or in the pcs and so we could just have one bit telling us which
type of reset to perform.

>  };
>  
>  static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
> @@ -1314,6 +1322,9 @@ static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
>                 return 0;
>         }
>  
> +       if (qmp->ufs_reset)
> +               reset_control_assert(qmp->ufs_reset);
> +
>         if (cfg->has_phy_com_ctrl) {
>                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
>                              SERDES_START | PCS_START);
> @@ -1351,6 +1362,33 @@ static int qcom_qmp_phy_init(struct phy *phy)
>  
>         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
>  
> +       if (cfg->has_ufsphy_reset) {
> +               /*
> +                * Get UFS reset, which is delayed until now to avoid a
> +                * circular dependency where UFS needs its PHY, but the PHY
> +                * needs this UFS reset.
> +                */
> +               if (!qmp->ufs_reset) {
> +                       qmp->ufs_reset =
> +                               devm_reset_control_get_exclusive(qmp->dev,
> +                                                                "ufsphy");
> +
> +                       if (IS_ERR(qmp->ufs_reset)) {
> +                               dev_err(qmp->dev,
> +                                       "failed to get UFS reset: %d\n",
> +                                       PTR_ERR(qmp->ufs_reset));
> +
> +                               ret = PTR_ERR(qmp->ufs_reset);

Do this ret conversion once and then print it after?

> +                               qmp->ufs_reset = NULL;
> +                               return ret;
> +                       }
> +               }
> +
> +               ret = reset_control_assert(qmp->ufs_reset);
> +               if (ret)
> +                       goto err_lane_rst;
> +       }
> +
>         ret = qcom_qmp_phy_com_init(qphy);
>         if (ret)
>                 return ret;

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v2 9/9] phy: qcom-ufs: Refactor all init steps into phy_poweron
  2019-01-23 22:11 ` [PATCH v2 9/9] phy: qcom-ufs: Refactor all init steps into phy_poweron Evan Green
@ 2019-02-01 18:43   ` Stephen Boyd
  2019-02-05 18:00     ` Evan Green
  0 siblings, 1 reply; 20+ messages in thread
From: Stephen Boyd @ 2019-02-01 18:43 UTC (permalink / raw)
  To: Andy Gross, Evan Green, Kishon Vijay Abraham I, Rob Herring
  Cc: Can Guo, Douglas Anderson, Asutosh Das, Vivek Gautam, Evan Green,
	Bjorn Andersson, Arnd Bergmann, Grygorii Strashko, Marc Gonzalez,
	linux-kernel, Martin K. Petersen

Quoting Evan Green (2019-01-23 14:11:37)
> The phy code was using implicit sequencing between the PHY driver
> and the UFS driver to implement certain hardware requirements.
> Specifically, the PHY reset register in the UFS controller needs
> to be deasserted before serdes start occurs in the PHY.
> 
> Before this change, the code was doing this by utilizing the two
> phy callbacks, phy_init and phy_poweron, as "init step 1" and

Nitpick: Can you please indicate functions with () and variables with
''? So write phy_init() and phy_poweron(), etc.

> "init step 2", where the UFS driver would deassert reset between
> these two steps.
> 
> This makes it challenging to power off the regulators in suspend,
> as regulators are initialized in init, not in poweron, but only
> poweroff is called during suspend, not exit.
> 
> Consolidate the initialization code into phy_poweron, and utilize
> the reset controller exported from the UFS driver to explicitly
> perform all the steps needed to initialize the PHY.

Also mention that a new callback is introduced, 'calibrate', that 
> 
> Signed-off-by: Evan Green <evgreen@chromium.org>

> diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-i.h b/drivers/phy/qualcomm/phy-qcom-ufs-i.h
> index f798fb64de94e..109ddd67be829 100644
> --- a/drivers/phy/qualcomm/phy-qcom-ufs-i.h
> +++ b/drivers/phy/qualcomm/phy-qcom-ufs-i.h
> @@ -19,6 +19,7 @@
>  #include <linux/clk.h>
>  #include <linux/phy/phy.h>
>  #include <linux/regulator/consumer.h>
> +#include <linux/reset.h>

Just forward declare struct reset_control instead of including this.

>  #include <linux/slab.h>
>  #include <linux/platform_device.h>
>  #include <linux/io.h>
> @@ -96,11 +97,10 @@ struct ufs_qcom_phy {
>         char name[UFS_QCOM_PHY_NAME_LEN];
>         struct ufs_qcom_phy_calibration *cached_regs;
>         int cached_regs_table_size;
> -       bool is_powered_on;
> -       bool is_started;
>         struct ufs_qcom_phy_specific_ops *phy_spec_ops;
>  
>         enum phy_mode mode;
> +       struct reset_control *ufs_reset;
>  };
>  
>  /**

For some reason I get the feeling that this patch should be combined
with something else from the controller. Does this complete the
conversion but the patches before this one sort of wreck the state of
reset and init/poweron phases so that they can't stand on their own?
Maybe if the reset was introduced, and then a patch to get the resets
was put in place, and then a final patch to rewrite the phy and
controller at the same time would make more sense to read.


^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v2 6/9] scsi: ufs: qcom: Expose the reset controller for PHY
  2019-02-01 17:56   ` Stephen Boyd
@ 2019-02-05 17:59     ` Evan Green
  0 siblings, 0 replies; 20+ messages in thread
From: Evan Green @ 2019-02-05 17:59 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: Andy Gross, Kishon Vijay Abraham I, Rob Herring, Can Guo,
	Douglas Anderson, Asutosh Das, Vivek Gautam,
	James E.J. Bottomley, Vinayak Holikatti, Martin K. Petersen,
	SCSI, LKML

On Fri, Feb 1, 2019 at 9:56 AM Stephen Boyd <swboyd@chromium.org> wrote:
>
> Quoting Evan Green (2019-01-23 14:11:34)
> > Expose a reset controller that the phy can use to perform its
> > initialization in a single callback.
> >
> > Also, change the use of the phy functions from ufs-qcom such that
> > phy_poweron actually fires up the phy, and phy_poweroff actually
> > powers it down.
>
> This looks like two patches. One introduces a reset controller and the
> other changes the phy functions somehow. Can this be split up and then
> the commit text for the second half to change the phy functions can
> explain a little more of the theory behind how it's OK to change the
> code flow that way?

Sure, I can split the change in two.

>
> >
> > Signed-off-by: Evan Green <evgreen@chromium.org>
> >
> > ---
> > Note: This change depends on the remaining changes in this series,
> > since UFS PHY reset now needs to be done by the PHY driver.
>
> What does it depend on? Is there a bisection hole introduced here? An by
> bisection hole I mean more than the problem that an older DT is used
> with this new code.

Everything still builds, but there is a functional bisection hole here
in that UFS won't come up if you have this change but not the
following changes. The problem is that this change removes the reset
assert/deassert from ufs-qcom, and it's not until the next change that
the PHY is taught to use the reset controller to do those required
resets. Technically it's "phy: qcom-qmp: Utilize UFS reset controller"
that does the needed reset assert/deassert for qmp-phy, and "phy:
qcom-ufs: Refactor all init steps into phy_poweron" for the older
phy-qcom-ufs.

I was trying to keep changes in different components separate. Let me
refactor it into a way that makes more sense from a functional
perspective. The downside is that a couple of changes will touch three
drivers (both PHYs and the UFS controller) in a single change. But the
upside is that it's probably easier to review, and there will be no
bisection hole.

>
> >
> > Changes in v2:
> > - Remove include of reset.h (Stephen)
>
> Usually we include headers in both the C file and the header files that
> use structs from header files. It wouldn't hurt to include
> reset-controller.h in the ufs-qcom.c file. For one thing, it would help
> a grep find reset controller drivers trim based on files ending in .c
> instead of having to figure out which C file includes the .h file where
> the reset-controller header is included.

Sure, will do.

>
> > - Fix error print of phy_power_on (Stephen)
> > - Comment for reset controller warnings on id != 0 (Stephen)
> > - Add static to ufs_qcom_reset_ops (Stephen).
> >
> >  drivers/scsi/ufs/Kconfig    |   1 +
> >  drivers/scsi/ufs/ufs-qcom.c | 111 ++++++++++++++++++++++--------------
> >  drivers/scsi/ufs/ufs-qcom.h |   4 ++
> >  3 files changed, 72 insertions(+), 44 deletions(-)
> >
> > diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
> > index 3aeadb14aae1e..277ed6ad71c9b 100644
> > --- a/drivers/scsi/ufs/ufs-qcom.c
> > +++ b/drivers/scsi/ufs/ufs-qcom.c
> > @@ -255,11 +260,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> >         if (is_rate_B)
> >                 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
> >
> > -       /* Assert PHY reset and apply PHY calibration values */
> > -       ufs_qcom_assert_reset(hba);
> > -       /* provide 1ms delay to let the reset pulse propagate */
> > -       usleep_range(1000, 1100);
> > -
> >         /* phy initialization - calibrate the phy */
> >         ret = phy_init(phy);
> >         if (ret) {
> > @@ -268,15 +268,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> >                 goto out;
> >         }
> >
> > -       /* De-assert PHY reset and start serdes */
> > -       ufs_qcom_deassert_reset(hba);
> > -
> > -       /*
> > -        * after reset deassertion, phy will need all ref clocks,
> > -        * voltage, current to settle down before starting serdes.
> > -        */
> > -       usleep_range(1000, 1100);
> > -
> >         /* power on phy - start serdes and phy's power and clocks */
> >         ret = phy_power_on(phy);
> >         if (ret) {
> > @@ -290,7 +281,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> >         return 0;
> >
> >  out_disable_phy:
> > -       ufs_qcom_assert_reset(hba);
> >         phy_exit(phy);
> >  out:
> >         return ret;
> > @@ -554,21 +544,10 @@ static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
> >                 ufs_qcom_disable_lane_clks(host);
> >                 phy_power_off(phy);
> >
> > -               /* Assert PHY soft reset */
> > -               ufs_qcom_assert_reset(hba);
> > -               goto out;
> > -       }
> > -
> > -       /*
> > -        * If UniPro link is not active, PHY ref_clk, main PHY analog power
> > -        * rail and low noise analog power rail for PLL can be switched off.
> > -        */
> > -       if (!ufs_qcom_is_link_active(hba)) {
> > +       } else if (!ufs_qcom_is_link_active(hba)) {
> >                 ufs_qcom_disable_lane_clks(host);
> > -               phy_power_off(phy);
> >         }
> >
> > -out:
> >         return ret;
> >  }
> >
> > @@ -578,21 +557,26 @@ static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
> >         struct phy *phy = host->generic_phy;
> >         int err;
> >
> > -       err = phy_power_on(phy);
> > -       if (err) {
> > -               dev_err(hba->dev, "%s: failed enabling regs, err = %d\n",
> > -                       __func__, err);
> > -               goto out;
> > -       }
> > +       if (ufs_qcom_is_link_off(hba)) {
> > +               err = phy_power_on(phy);
> > +               if (err) {
> > +                       dev_err(hba->dev, "%s: failed PHY power on: %d\n",
> > +                               __func__, err);
> > +                       return err;
> > +               }
> >
> > -       err = ufs_qcom_enable_lane_clks(host);
> > -       if (err)
> > -               goto out;
> > +               err = ufs_qcom_enable_lane_clks(host);
> > +               if (err)
> > +                       return err;
> >
> > -       hba->is_sys_suspended = false;
> > +       } else if (!ufs_qcom_is_link_active(hba)) {
> > +               err = ufs_qcom_enable_lane_clks(host);
> > +               if (err)
> > +                       return err;
> > +       }
> >
> > -out:
> > -       return err;
> > +       hba->is_sys_suspended = false;
> > +       return 0;
> >  }
> >
> >  struct ufs_qcom_dev_params {
> > @@ -1118,8 +1102,6 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
> >                 return 0;
> >
> >         if (on && (status == POST_CHANGE)) {
> > -               phy_power_on(host->generic_phy);
> > -
> >                 /* enable the device ref clock for HS mode*/
> >                 if (ufshcd_is_hs_mode(&hba->pwr_info))
> >                         ufs_qcom_dev_ref_clk_ctrl(host, true);
> > @@ -1131,9 +1113,6 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
> >                 if (!ufs_qcom_is_link_active(hba)) {
> >                         /* disable device ref_clk */
> >                         ufs_qcom_dev_ref_clk_ctrl(host, false);
> > -
> > -                       /* powering off PHY during aggressive clk gating */
> > -                       phy_power_off(host->generic_phy);
> >                 }
> >
> >                 vote = host->bus_vote.min_bw_vote;
>
> All the above hunks should probably be another patch with a motivation
> and explanation about what's going on in the commit text.

Ok.

>
> > @@ -1147,6 +1126,41 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
> >         return err;
> >  }
> >
> > +static int
> > +ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
> > +{
> > +       struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
> > +
> > +       /* Currently this code only knows about a single reset. */
>
> Ultra nitpick: Drop the full stop to be consistent with single line
> comment style in this function?

Ok. Maybe I'll add the period to the other comment in this function,
so that the two functions are consistent with each other.

>
> > +       WARN_ON(id);
> > +       ufs_qcom_assert_reset(host->hba);
> > +       /* provide 1ms delay to let the reset pulse propagate */
> > +       usleep_range(1000, 1100);
> > +       return 0;
> > +}
> > +
> > +static int
> > +ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
> > +{
> > +       struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
> > +
> > +       /* Currently this code only knows about a single reset. */
>
> Well now it's different!

Not anymore!

>
> > +       WARN_ON(id);
> > +       ufs_qcom_deassert_reset(host->hba);
> > +
> > +       /*
> > +        * after reset deassertion, phy will need all ref clocks,
> > +        * voltage, current to settle down before starting serdes.
> > +        */
> > +       usleep_range(1000, 1100);
> > +       return 0;
> > +}
> > +
> > +const static struct reset_control_ops ufs_qcom_reset_ops = {
>
> const goes after static. Funny, there are some other grep hits for
> 'const static' in the kernel, but it's a small minority. Maybe those
> should be fixed.

Ok. Apparently there are historical reasons why nearly all compilers
accept any order of these two classes of keywords. Which means I never
remember what the right way is :)

>
> > +       .assert = ufs_qcom_reset_assert,
> > +       .deassert = ufs_qcom_reset_deassert,
> > +};
> > +
> >  #define        ANDROID_BOOT_DEV_MAX    30
> >  static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
> >
>
> Ooh Android!
>
> > @@ -1191,6 +1205,15 @@ static int ufs_qcom_init(struct ufs_hba *hba)
> >         host->hba = hba;
> >         ufshcd_set_variant(hba, host);
> >
> > +       /* Fire up the reset controller. Failure here is non-fatal. */
> > +       host->rcdev.of_node = dev->of_node;
> > +       host->rcdev.ops = &ufs_qcom_reset_ops;
> > +       host->rcdev.owner = dev->driver->owner;
> > +       host->rcdev.nr_resets = 1;
> > +       err = devm_reset_controller_register(dev, &host->rcdev);
> > +       if (err)
> > +               dev_warn(dev, "Failed to register reset controller\n");
>
> reset err to 0 because we don't care to fail here (it's just a warn, not
> a dev_err)?

Sure.

>
> > +
> >         /*
> >          * voting/devoting device ref_clk source is time consuming hence
> >          * skip devoting it during aggressive clock gating. This clock

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v2 7/9] phy: qcom-qmp: Utilize UFS reset controller
  2019-02-01 18:00   ` Stephen Boyd
@ 2019-02-05 18:00     ` Evan Green
  0 siblings, 0 replies; 20+ messages in thread
From: Evan Green @ 2019-02-05 18:00 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: Andy Gross, Kishon Vijay Abraham I, Rob Herring, Can Guo,
	Douglas Anderson, Asutosh Das, Vivek Gautam, Jeffrey Hugo, LKML,
	Manu Gautam

On Fri, Feb 1, 2019 at 10:00 AM Stephen Boyd <swboyd@chromium.org> wrote:
>
> Quoting Evan Green (2019-01-23 14:11:35)
> > @@ -1144,6 +1150,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
> >
> >         .is_dual_lane_phy       = true,
> >         .no_pcs_sw_reset        = true,
> > +
> > +       .has_ufsphy_reset       = true,
>
> Is this the same as .no_pcs_sw_reset implying that .has_ufsphy_reset? Or
> it's possible to have no resets at all? I'd think there's a reset in the
> phy or in the pcs and so we could just have one bit telling us which
> type of reset to perform.

Ok. I guess pcs_sw_reset is the same reset as this bit that seems to
bubble up in the ufs-qcom controller? If some new crazy qcom chip
comes up that has both resets or no resets, this should be pretty
simple to disentangle.

>
> >  };
> >
> >  static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
> > @@ -1314,6 +1322,9 @@ static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
> >                 return 0;
> >         }
> >
> > +       if (qmp->ufs_reset)
> > +               reset_control_assert(qmp->ufs_reset);
> > +
> >         if (cfg->has_phy_com_ctrl) {
> >                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
> >                              SERDES_START | PCS_START);
> > @@ -1351,6 +1362,33 @@ static int qcom_qmp_phy_init(struct phy *phy)
> >
> >         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
> >
> > +       if (cfg->has_ufsphy_reset) {
> > +               /*
> > +                * Get UFS reset, which is delayed until now to avoid a
> > +                * circular dependency where UFS needs its PHY, but the PHY
> > +                * needs this UFS reset.
> > +                */
> > +               if (!qmp->ufs_reset) {
> > +                       qmp->ufs_reset =
> > +                               devm_reset_control_get_exclusive(qmp->dev,
> > +                                                                "ufsphy");
> > +
> > +                       if (IS_ERR(qmp->ufs_reset)) {
> > +                               dev_err(qmp->dev,
> > +                                       "failed to get UFS reset: %d\n",
> > +                                       PTR_ERR(qmp->ufs_reset));
> > +
> > +                               ret = PTR_ERR(qmp->ufs_reset);
>
> Do this ret conversion once and then print it after?

Yeah, good idea.

>
> > +                               qmp->ufs_reset = NULL;
> > +                               return ret;
> > +                       }
> > +               }
> > +
> > +               ret = reset_control_assert(qmp->ufs_reset);
> > +               if (ret)
> > +                       goto err_lane_rst;
> > +       }
> > +
> >         ret = qcom_qmp_phy_com_init(qphy);
> >         if (ret)
> >                 return ret;

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v2 9/9] phy: qcom-ufs: Refactor all init steps into phy_poweron
  2019-02-01 18:43   ` Stephen Boyd
@ 2019-02-05 18:00     ` Evan Green
  0 siblings, 0 replies; 20+ messages in thread
From: Evan Green @ 2019-02-05 18:00 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: Andy Gross, Kishon Vijay Abraham I, Rob Herring, Can Guo,
	Douglas Anderson, Asutosh Das, Vivek Gautam, Bjorn Andersson,
	Arnd Bergmann, Grygorii Strashko, Marc Gonzalez, LKML,
	Martin K. Petersen

On Fri, Feb 1, 2019 at 10:43 AM Stephen Boyd <swboyd@chromium.org> wrote:
>
> Quoting Evan Green (2019-01-23 14:11:37)
> > The phy code was using implicit sequencing between the PHY driver
> > and the UFS driver to implement certain hardware requirements.
> > Specifically, the PHY reset register in the UFS controller needs
> > to be deasserted before serdes start occurs in the PHY.
> >
> > Before this change, the code was doing this by utilizing the two
> > phy callbacks, phy_init and phy_poweron, as "init step 1" and
>
> Nitpick: Can you please indicate functions with () and variables with
> ''? So write phy_init() and phy_poweron(), etc.

Sure.

>
> > "init step 2", where the UFS driver would deassert reset between
> > these two steps.
> >
> > This makes it challenging to power off the regulators in suspend,
> > as regulators are initialized in init, not in poweron, but only
> > poweroff is called during suspend, not exit.
> >
> > Consolidate the initialization code into phy_poweron, and utilize
> > the reset controller exported from the UFS driver to explicitly
> > perform all the steps needed to initialize the PHY.
>
> Also mention that a new callback is introduced, 'calibrate', that
> >
> > Signed-off-by: Evan Green <evgreen@chromium.org>
>
> > diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-i.h b/drivers/phy/qualcomm/phy-qcom-ufs-i.h
> > index f798fb64de94e..109ddd67be829 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-ufs-i.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-ufs-i.h
> > @@ -19,6 +19,7 @@
> >  #include <linux/clk.h>
> >  #include <linux/phy/phy.h>
> >  #include <linux/regulator/consumer.h>
> > +#include <linux/reset.h>
>
> Just forward declare struct reset_control instead of including this.

It looks like convention in this driver is to include everything in
this header, phy-qcom-ufs.c includes nothing but this file, and
similarly for the 14nm and 20nm variants. So maybe I should stay
following suit rather than being that one dude who plops his include
in a different spot.

>
> >  #include <linux/slab.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/io.h>
> > @@ -96,11 +97,10 @@ struct ufs_qcom_phy {
> >         char name[UFS_QCOM_PHY_NAME_LEN];
> >         struct ufs_qcom_phy_calibration *cached_regs;
> >         int cached_regs_table_size;
> > -       bool is_powered_on;
> > -       bool is_started;
> >         struct ufs_qcom_phy_specific_ops *phy_spec_ops;
> >
> >         enum phy_mode mode;
> > +       struct reset_control *ufs_reset;
> >  };
> >
> >  /**
>
> For some reason I get the feeling that this patch should be combined
> with something else from the controller. Does this complete the
> conversion but the patches before this one sort of wreck the state of
> reset and init/poweron phases so that they can't stand on their own?
> Maybe if the reset was introduced, and then a patch to get the resets
> was put in place, and then a final patch to rewrite the phy and
> controller at the same time would make more sense to read.

Yeah, let me try this refactoring.

^ permalink raw reply	[flat|nested] 20+ messages in thread

end of thread, other threads:[~2019-02-05 18:01 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-23 22:11 [PATCH v2 0/9] phy: qcom-ufs: Enable regulators to be off in suspend Evan Green
2019-01-23 22:11 ` [PATCH v2 1/9] dt-bindings: ufs: Add #reset-cells for Qualcomm controllers Evan Green
2019-01-30 18:56   ` Rob Herring
2019-02-01 17:41   ` Stephen Boyd
2019-01-23 22:11 ` [PATCH v2 2/9] dt-bindings: phy-qcom-qmp: Add UFS PHY reset Evan Green
2019-02-01 17:41   ` Stephen Boyd
2019-01-23 22:11 ` [PATCH v2 3/9] dt-bindings: phy: qcom-ufs: Add resets property Evan Green
2019-02-01 17:41   ` Stephen Boyd
2019-01-23 22:11 ` [PATCH v2 4/9] arm64: dts: sdm845: Add UFS PHY reset Evan Green
2019-01-23 22:11 ` [PATCH v2 5/9] arm64: dts: msm8996: Add UFS PHY reset controller Evan Green
2019-01-23 22:11 ` [PATCH v2 6/9] scsi: ufs: qcom: Expose the reset controller for PHY Evan Green
2019-02-01 17:56   ` Stephen Boyd
2019-02-05 17:59     ` Evan Green
2019-01-23 22:11 ` [PATCH v2 7/9] phy: qcom-qmp: Utilize UFS reset controller Evan Green
2019-02-01 18:00   ` Stephen Boyd
2019-02-05 18:00     ` Evan Green
2019-01-23 22:11 ` [PATCH v2 8/9] phy: qcom-qmp: Move UFS phy to phy_poweron/off Evan Green
2019-01-23 22:11 ` [PATCH v2 9/9] phy: qcom-ufs: Refactor all init steps into phy_poweron Evan Green
2019-02-01 18:43   ` Stephen Boyd
2019-02-05 18:00     ` Evan Green

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