[PATCH 0/5] Add initial Bitmain BM1880 SoC/Board support

[PATCH 0/5] Add initial Bitmain BM1880 SoC/Board support

[Manivannan Sadhasivam]

Hello,

This patchset adds initial support for Bitmain BM1880 SoC and Sophon
Edge board. BM1880 SoC consists of a Dual Core ARM Cortex A53 Application
processor subsystem, a single core RISC-V subsystem and a Tensor
Processor subsystem. This patchset adds support for only ARM Cortex
A53 Application processor subsystem with UART, which enables the board to
boot into initramfs with 2 CPUs.

Thanks,
Mani

Manivannan Sadhasivam (5):
  dt-bindings: arm: Document Bitmain BM1880 SoC
  arm64: Add ARCH_BITMAIN platform
  arm64: dts: bitmain: Add BM1880 SoC support
  arm64: dts: bitmain: Add Sophon Egde board support
  MAINTAINERS: Add entry for Bitmain SoC platform

 .../devicetree/bindings/arm/bitmain.yaml      |  18 +++
 MAINTAINERS                                   |   7 ++
 arch/arm64/Kconfig.platforms                  |   5 +
 arch/arm64/boot/dts/Makefile                  |   1 +
 arch/arm64/boot/dts/bitmain/Makefile          |   3 +
 .../boot/dts/bitmain/bm1880-sophon-edge.dts   |  50 ++++++++
 arch/arm64/boot/dts/bitmain/bm1880.dtsi       | 119 ++++++++++++++++++
 7 files changed, 203 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bitmain.yaml
 create mode 100644 arch/arm64/boot/dts/bitmain/Makefile
 create mode 100644 arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
 create mode 100644 arch/arm64/boot/dts/bitmain/bm1880.dtsi

-- 
2.17.1

[PATCH 1/5] dt-bindings: arm: Document Bitmain BM1880 SoC

[Manivannan Sadhasivam]

Document Bitmain BM1880 SoC from Bitmain Technologies Ltd along with the
Sophon Edge board.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 .../devicetree/bindings/arm/bitmain.yaml       | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bitmain.yaml

diff --git a/Documentation/devicetree/bindings/arm/bitmain.yaml b/Documentation/devicetree/bindings/arm/bitmain.yaml
new file mode 100644
index 000000000000..0efdb4ac028e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bitmain.yaml
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bitmain.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bitmain platform device tree bindings
+
+maintainers:
+  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+properties:
+  compatible:
+    items:
+      - enum:
+        - bitmain,sophon-edge
+      - const: bitmain,bm1880
+...
-- 
2.17.1

[PATCH 2/5] arm64: Add ARCH_BITMAIN platform

[Manivannan Sadhasivam]

Add ARCH_BITMAIN for supporting Bitmain SoC platforms.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/Kconfig.platforms | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 251ecf34cb02..6bb7db9126f7 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -52,6 +52,11 @@ config ARCH_BERLIN
 	help
 	  This enables support for Marvell Berlin SoC Family
 
+config ARCH_BITMAIN
+	bool "Bitmain SoC Platforms"
+	help
+	  This enables support for the Bitmain SoC Family.
+
 config ARCH_BRCMSTB
 	bool "Broadcom Set-Top-Box SoCs"
 	select BRCMSTB_L2_IRQ
-- 
2.17.1

[PATCH 3/5] arm64: dts: bitmain: Add BM1880 SoC support

[Manivannan Sadhasivam]

Add devicetree support for Bitmain BM1880 SoC, consisting of a Dual
core ARM Cortex A53 subsystem, a Single core RISC-V subsystem and a Tensor
Processor subsystem. Only ARM Cortex A53 Application processor subsystem
support is enabled for now.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/Makefile            |   1 +
 arch/arm64/boot/dts/bitmain/bm1880.dtsi | 119 ++++++++++++++++++++++++
 2 files changed, 120 insertions(+)
 create mode 100644 arch/arm64/boot/dts/bitmain/bm1880.dtsi

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 4690364d584b..5bc7533a12c7 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -7,6 +7,7 @@ subdir-y += amd
 subdir-y += amlogic
 subdir-y += apm
 subdir-y += arm
+subdir-y += bitmain
 subdir-y += broadcom
 subdir-y += cavium
 subdir-y += exynos
diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
new file mode 100644
index 000000000000..55a4769e0de2
--- /dev/null
+++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Linaro Ltd.
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "bitmain,bm1880";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x1>;
+			enable-method = "psci";
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secmon@100000000 {
+			reg = <0x1 0x00000000 0x0 0x20000>;
+			no-map;
+		};
+
+		jpu@130000000 {
+			reg = <0x1 0x30000000 0x0 0x08000000>; // 128M
+			no-map;
+		};
+
+		vpu@138000000 {
+			reg = <0x1 0x38000000 0x0 0x08000000>; // 128M
+			no-map;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gic: interrupt-controller@50001000 {
+			compatible = "arm,gic-400";
+			reg = <0x0 0x50001000 0x0 0x1000>,
+			      <0x0 0x50002000 0x0 0x2000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		uart0: serial@58018000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x58018000 0x0 0x2000>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart1: serial@5801A000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x5801a000 0x0 0x2000>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart2: serial@5801C000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x5801c000 0x0 0x2000>;
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart3: serial@5801E000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x5801e000 0x0 0x2000>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+	};
+};
-- 
2.17.1

[PATCH 4/5] arm64: dts: bitmain: Add Sophon Egde board support

[Manivannan Sadhasivam]

Add devicetree support for Sophon Edge board from Bitmain based on
BM1880 SoC. This board is one of the 96Boards Consumer and AI platform.
More information about this board can be found in 96Boards product page:

https://www.96boards.org/documentation/consumer/sophon-edge/

Only UART peripheral support is enabled for now.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/bitmain/Makefile          |  3 ++
 .../boot/dts/bitmain/bm1880-sophon-edge.dts   | 50 +++++++++++++++++++
 2 files changed, 53 insertions(+)
 create mode 100644 arch/arm64/boot/dts/bitmain/Makefile
 create mode 100644 arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts

diff --git a/arch/arm64/boot/dts/bitmain/Makefile b/arch/arm64/boot/dts/bitmain/Makefile
new file mode 100644
index 000000000000..be90a6071be0
--- /dev/null
+++ b/arch/arm64/boot/dts/bitmain/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+dtb-$(CONFIG_ARCH_BITMAIN) += bm1880-sophon-edge.dtb
diff --git a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
new file mode 100644
index 000000000000..6a3255597138
--- /dev/null
+++ b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Linaro Ltd.
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "bm1880.dtsi"
+
+/ {
+	compatible = "bitmain,sophon-edge", "bitmain,bm1880";
+	model = "Sophon Edge";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart2;
+		serial2 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB
+	};
+
+	uart_clk: uart-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <500000000>;
+		#clock-cells = <0>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+	clocks = <&uart_clk>;
+};
+
+&uart1 {
+	status = "okay";
+	clocks = <&uart_clk>;
+};
+
+&uart2 {
+	status = "okay";
+	clocks = <&uart_clk>;
+};
-- 
2.17.1

[PATCH 5/5] MAINTAINERS: Add entry for Bitmain SoC platform

[Manivannan Sadhasivam]

Add MAINTAINERS entry for Bitmain SoC platform with myself as the
Maintainer.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 MAINTAINERS | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 51029a425dbe..da85ffe5e3f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1372,6 +1372,13 @@ F:	arch/arm/mach-aspeed/
 F:	arch/arm/boot/dts/aspeed-*
 N:	aspeed
 
+ARM/BITMAIN ARCHITECTURE
+M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:	Maintained
+F:	arch/arm64/boot/dts/bitmain/
+F:	Documentation/devicetree/bindings/arm/bitmain.yaml
+
 ARM/CALXEDA HIGHBANK ARCHITECTURE
 M:	Rob Herring <robh@kernel.org>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-- 
2.17.1

Re: [PATCH 0/5] Add initial Bitmain BM1880 SoC/Board support

[Andrew Lunn]

On Sat, Jan 26, 2019 at 09:40:36AM +0530, Manivannan Sadhasivam wrote:
> Hello,
> 
> This patchset adds initial support for Bitmain BM1880 SoC and Sophon
> Edge board. BM1880 SoC consists of a Dual Core ARM Cortex A53 Application
> processor subsystem, a single core RISC-V subsystem and a Tensor
> Processor subsystem.

Hi Manivannan

Interesting combination of CPUs. 

> This patchset adds support for only ARM Cortex A53 Application
> processor subsystem with UART, which enables the board to boot into
> initramfs with 2 CPUs.

Looking forward, what sharing do you expect at the device tree level?

Looking at 

https://sophon-file.bitmain.com.cn/sophon-prod/drive/18/11/06/19/BM1880%20product%20brief%20V0.04_Chinese%20versionV0.06.pdf

it appears all the devices can be shared between the CPUs. So do you
plan to have a shared .dtsi file somewhere? 

Is ARCH_BITMAIN going to be both ARM64 and RISC-V?

   Thanks
	Andrew

Re: [PATCH 0/5] Add initial Bitmain BM1880 SoC/Board support

[Manivannan Sadhasivam]

Hi Andrew,

On Sat, Jan 26, 2019 at 04:03:20PM +0100, Andrew Lunn wrote:
> On Sat, Jan 26, 2019 at 09:40:36AM +0530, Manivannan Sadhasivam wrote:
> > Hello,
> > 
> > This patchset adds initial support for Bitmain BM1880 SoC and Sophon
> > Edge board. BM1880 SoC consists of a Dual Core ARM Cortex A53 Application
> > processor subsystem, a single core RISC-V subsystem and a Tensor
> > Processor subsystem.
> 
> Hi Manivannan
> 
> Interesting combination of CPUs. 
> 
> > This patchset adds support for only ARM Cortex A53 Application
> > processor subsystem with UART, which enables the board to boot into
> > initramfs with 2 CPUs.
> 
> Looking forward, what sharing do you expect at the device tree level?
> 
> Looking at 
> 
> https://sophon-file.bitmain.com.cn/sophon-prod/drive/18/11/06/19/BM1880%20product%20brief%20V0.04_Chinese%20versionV0.06.pdf
> 
> it appears all the devices can be shared between the CPUs. So do you
> plan to have a shared .dtsi file somewhere? 
> 
> Is ARCH_BITMAIN going to be both ARM64 and RISC-V?
> 

We don't have any plan to add support for RISC-V subsystem. Moreover,
from the SoC product brief it look like the RISC-V core is a MCU grade
core, so I doubt whether we can run linux on it! It might be a candidate
for RTOS.

For now, ARCH_BITMAIN is going to have only ARM64 support.

Thanks,
Mani

>    Thanks
> 	Andrew

Re: [PATCH 1/5] dt-bindings: arm: Document Bitmain BM1880 SoC

[Rob Herring]

On Fri, Jan 25, 2019 at 10:11 PM Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> Document Bitmain BM1880 SoC from Bitmain Technologies Ltd along with the
> Sophon Edge board.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  .../devicetree/bindings/arm/bitmain.yaml       | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/bitmain.yaml

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 0/5] Add initial Bitmain BM1880 SoC/Board support

[Arnd Bergmann]

On Sat, Jan 26, 2019 at 5:11 AM Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> Hello,
>
> This patchset adds initial support for Bitmain BM1880 SoC and Sophon
> Edge board. BM1880 SoC consists of a Dual Core ARM Cortex A53 Application
> processor subsystem, a single core RISC-V subsystem and a Tensor
> Processor subsystem. This patchset adds support for only ARM Cortex
> A53 Application processor subsystem with UART, which enables the board to
> boot into initramfs with 2 CPUs.

Nice work! All patches in this series

Acked-by: Arnd Bergmann <arnd@arndb.de>

Re: [PATCH 0/5] Add initial Bitmain BM1880 SoC/Board support

[Manivannan Sadhasivam]

Hi Arnd,

On Sun, Jan 27, 2019 at 10:24:09AM +0100, Arnd Bergmann wrote:
> On Sat, Jan 26, 2019 at 5:11 AM Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> >
> > Hello,
> >
> > This patchset adds initial support for Bitmain BM1880 SoC and Sophon
> > Edge board. BM1880 SoC consists of a Dual Core ARM Cortex A53 Application
> > processor subsystem, a single core RISC-V subsystem and a Tensor
> > Processor subsystem. This patchset adds support for only ARM Cortex
> > A53 Application processor subsystem with UART, which enables the board to
> > boot into initramfs with 2 CPUs.
> 
> Nice work! All patches in this series
> 
> Acked-by: Arnd Bergmann <arnd@arndb.de>

Thanks. What is the merge strategy for this patchset? Shall I send a
Pull Request to arm@kernel.org with topic branches?

Regards,
Mani

Re: [PATCH 0/5] Add initial Bitmain BM1880 SoC/Board support

[Arnd Bergmann]

On Fri, Feb 1, 2019, 04:50 Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org wrote:
> On Sun, Jan 27, 2019 at 10:24:09AM +0100, Arnd Bergmann wrote:
> > On Sat, Jan 26, 2019 at 5:11 AM Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote:
> > >
> > > This patchset adds initial support for Bitmain BM1880 SoC and Sophon
> > > Edge board. BM1880 SoC consists of a Dual Core ARM Cortex A53 Application
> > > processor subsystem, a single core RISC-V subsystem and a Tensor
> > > Processor subsystem. This patchset adds support for only ARM Cortex
> > > A53 Application processor subsystem with UART, which enables the board to
> > > boot into initramfs with 2 CPUs.
> >
> > Nice work! All patches in this series
> >
> > Acked-by: Arnd Bergmann <arnd@arndb.de>
>
> Thanks. What is the merge strategy for this patchset? Shall I send a
> Pull Request to arm@kernel.org with topic branches?

I think we should take new platforms as a single topic branch separate
from the normal branches, so please send a single pull request for this
one.

Also, if you have drivers that are closely tied to this platform, that
branch include those as well, provided that you have an Ack from the
respective subsystem maintainers.

     Arnd