From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Nicolas Boichat <drinkcat@chromium.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Rob Herring <robh@kernel.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
Fan Chen <fan.chen@mediatek.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<srv_heupstream@mediatek.com>, <stable@vger.kernel.org>,
Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [PATCH v4 00/12] Mediatek MT8183 clock and scpsys support
Date: Fri, 1 Feb 2019 16:30:04 +0800 [thread overview]
Message-ID: <20190201083016.25856-2-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <20190201083016.25856-1-weiyi.lu@mediatek.com>
This series is based on v5.0-rc1 and most of changes are extracted from series below
(clock/scpsys common changes for both MT8183 & MT6765)
https://patchwork.kernel.org/patch/10528495/
(clock support of MT8183)
https://patchwork.kernel.org/patch/10549891/
The whole series is composed of
clock common changes for both MT8183 & MT6765 (PATCH 1-3),
scpsys common changes for both MT8183 & MT6765 (PATCH 4),
clock support of MT8183 (PATCH 5-8),
scpsys support of MT8183 (PATCH 9-11) and
resend a clock patch long time ago(PTACH 12).
change sinve v3:
- add fix tag.
- small change of mtk_clk_mux data structure.
- use of_property_for_each_string to iterate dependent subsys clock of power domain.
- document critical clocks.
- reduce some clock register error log.
- few coding style fix.
change sinve v2:
- refine for implementation consistency of mtk clk mux.
- separate the onoff API into enable/disable API for mtk scpsys.
- resend a patch about PLL rate changing.
changes since v1:
- refine for better code quality.
- some minor bug fix of clock part, like incorrect control address
and missing clocks.
James Liao (1):
clk: mediatek: Allow changing PLL rate when it is off
Owen Chen (4):
clk: mediatek: Disable tuner_en before change PLL rate
clk: mediatek: add new clkmux register API
clk: mediatek: add configurable pcwibits and fmin to mtk_pll_data
soc: mediatek: add new flow for mtcmos power.
Weiyi Lu (7):
dt-bindings: ARM: Mediatek: Document bindings for MT8183
clk: mediatek: Add dt-bindings for MT8183 clocks
clk: mediatek: Add flags support for mtk_gate data
clk: mediatek: Add MT8183 clock support
dt-bindings: soc: fix typo of MT8173 power dt-bindings
dt-bindings: soc: Add MT8183 power dt-bindings
soc: mediatek: Add MT8183 scpsys support
.../arm/mediatek/mediatek,apmixedsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,audsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,camsys.txt | 22 +
.../bindings/arm/mediatek/mediatek,imgsys.txt | 1 +
.../arm/mediatek/mediatek,infracfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,ipu.txt | 43 +
.../bindings/arm/mediatek/mediatek,mcucfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,mfgcfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,mmsys.txt | 1 +
.../arm/mediatek/mediatek,topckgen.txt | 1 +
.../arm/mediatek/mediatek,vdecsys.txt | 1 +
.../arm/mediatek/mediatek,vencsys.txt | 1 +
.../bindings/soc/mediatek/scpsys.txt | 14 +
drivers/clk/mediatek/Kconfig | 75 +
drivers/clk/mediatek/Makefile | 15 +-
drivers/clk/mediatek/clk-gate.c | 5 +-
drivers/clk/mediatek/clk-gate.h | 17 +-
drivers/clk/mediatek/clk-mt8183-audio.c | 105 ++
drivers/clk/mediatek/clk-mt8183-cam.c | 63 +
drivers/clk/mediatek/clk-mt8183-img.c | 63 +
drivers/clk/mediatek/clk-mt8183-ipu0.c | 56 +
drivers/clk/mediatek/clk-mt8183-ipu1.c | 56 +
drivers/clk/mediatek/clk-mt8183-ipu_adl.c | 54 +
drivers/clk/mediatek/clk-mt8183-ipu_conn.c | 123 ++
drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 54 +
drivers/clk/mediatek/clk-mt8183-mm.c | 111 ++
drivers/clk/mediatek/clk-mt8183-vdec.c | 67 +
drivers/clk/mediatek/clk-mt8183-venc.c | 59 +
drivers/clk/mediatek/clk-mt8183.c | 1285 +++++++++++++++++
drivers/clk/mediatek/clk-mtk.c | 3 +-
drivers/clk/mediatek/clk-mtk.h | 3 +
drivers/clk/mediatek/clk-mux.c | 223 +++
drivers/clk/mediatek/clk-mux.h | 89 ++
drivers/clk/mediatek/clk-pll.c | 53 +-
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mtk-scpsys-ext.c | 99 ++
drivers/soc/mediatek/mtk-scpsys.c | 602 ++++++--
include/dt-bindings/clock/mt8183-clk.h | 422 ++++++
include/dt-bindings/power/mt8173-power.h | 6 +-
include/dt-bindings/power/mt8183-power.h | 26 +
include/linux/soc/mediatek/scpsys-ext.h | 39 +
41 files changed, 3757 insertions(+), 107 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt
create mode 100644 drivers/clk/mediatek/clk-mt8183-audio.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-cam.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-img.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu0.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu1.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu_adl.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu_conn.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-mfgcfg.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-mm.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-vdec.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-venc.c
create mode 100644 drivers/clk/mediatek/clk-mt8183.c
create mode 100644 drivers/clk/mediatek/clk-mux.c
create mode 100644 drivers/clk/mediatek/clk-mux.h
create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
create mode 100644 include/dt-bindings/clock/mt8183-clk.h
create mode 100644 include/dt-bindings/power/mt8183-power.h
create mode 100644 include/linux/soc/mediatek/scpsys-ext.h
--
2.18.0
next prev parent reply other threads:[~2019-02-01 8:31 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-01 8:30 [PATCH v4 00/12] Mediatek MT8183 clock and scpsys support Weiyi Lu
2019-02-01 8:30 ` Weiyi Lu [this message]
2019-02-20 19:18 ` Stephen Boyd
2019-02-21 8:36 ` Matthias Brugger
2019-02-22 7:48 ` Stephen Boyd
2019-02-26 4:00 ` Weiyi Lu
2019-02-26 17:45 ` Stephen Boyd
2019-02-01 8:30 ` [PATCH v4 01/12] clk: mediatek: Disable tuner_en before change PLL rate Weiyi Lu
2019-02-26 15:59 ` Matthias Brugger
2019-02-27 3:51 ` Weiyi Lu
2019-02-27 4:39 ` Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 02/12] clk: mediatek: add new clkmux register API Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 03/12] clk: mediatek: add configurable pcwibits and fmin to mtk_pll_data Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 04/12] soc: mediatek: add new flow for mtcmos power Weiyi Lu
2019-02-08 18:30 ` Matthias Brugger
2019-02-01 8:30 ` [PATCH v4 05/12] dt-bindings: ARM: Mediatek: Document bindings for MT8183 Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 06/12] clk: mediatek: Add dt-bindings for MT8183 clocks Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 07/12] clk: mediatek: Add flags support for mtk_gate data Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 08/12] clk: mediatek: Add MT8183 clock support Weiyi Lu
2019-02-26 17:50 ` Stephen Boyd
2019-02-27 2:51 ` Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 09/12] dt-bindings: soc: fix typo of MT8173 power dt-bindings Weiyi Lu
2019-02-07 15:35 ` Matthias Brugger
2019-02-01 8:30 ` [PATCH v4 10/12] dt-bindings: soc: Add MT8183 " Weiyi Lu
2019-02-08 18:33 ` Matthias Brugger
2019-02-01 8:30 ` [PATCH v4 11/12] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 12/12] clk: mediatek: Allow changing PLL rate when it is off Weiyi Lu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190201083016.25856-2-weiyi.lu@mediatek.com \
--to=weiyi.lu@mediatek.com \
--cc=drinkcat@chromium.org \
--cc=fan.chen@mediatek.com \
--cc=jamesjj.liao@mediatek.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=robh@kernel.org \
--cc=sboyd@codeaurora.org \
--cc=srv_heupstream@mediatek.com \
--cc=stable@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).