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Mon, 04 Feb 2019 01:13:35 -0800 (PST) Received: from phenom.ffwll.local ([2a02:168:569e:0:3106:d637:d723:e855]) by smtp.gmail.com with ESMTPSA id 49sm4176271edz.59.2019.02.04.01.13.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 04 Feb 2019 01:13:34 -0800 (PST) Date: Mon, 4 Feb 2019 10:13:32 +0100 From: Daniel Vetter To: Alex Deucher Cc: Daniel Vetter , Stephen Rothwell , Dave Airlie , Linux Kernel Mailing List , DRI , Leo Li , Linux Next Mailing List , Kent Russell , Alex Deucher , Nicholas Kazlauskas , Ken Chalmers Subject: Re: linux-next: Fixes tags need some work in the drm tree Message-ID: <20190204091332.GJ3271@phenom.ffwll.local> Mail-Followup-To: Alex Deucher , Stephen Rothwell , Dave Airlie , Linux Kernel Mailing List , DRI , Leo Li , Linux Next Mailing List , Kent Russell , Alex Deucher , Nicholas Kazlauskas , Ken Chalmers References: <20190201105736.1428c9fc@canb.auug.org.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Operating-System: Linux phenom 4.19.0-1-amd64 User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 01, 2019 at 03:34:46PM -0500, Alex Deucher wrote: > On Fri, Feb 1, 2019 at 5:05 AM Daniel Vetter wrote: > > > > On Fri, Feb 1, 2019 at 12:57 AM Stephen Rothwell wrote: > > > > > > Hi all, > > > > > > In commit > > > > > > a93587b31e34 ("drm/amd/display: Only get the connector state for VRR when toggled") > > > > > > Fixes tag > > > > > > Fixes: 3cc22f281318 ("drm/amdgpu: Set FreeSync state using drm VRR properties") > > > > > > has these problem(s): > > > > > > - Target SHA1 does not exist > > > > > > Maybe instead: > > > > > > FIxes: bb47de736661 ("drm/amdgpu: Set FreeSync state using drm VRR properties") > > > > > > In commit > > > > > > 32e61361b82e ("drm/amd/display: Fix 64-bit division for 32-bit builds") > > > > > > Fixes tag > > > > > > Fixes: https://lists.freedesktop.org/archives/dri-devel/2018-December/201008.html > > > > > > has these problem(s): > > > > > > - No SHA1 recognised > > > > > > Maybe instead: > > > > > > Fixes: 80604e27bc9 ("drm/amd/display: Use 100 Hz precision for pipe pixel clocks") > > > > > > In commit > > > > > > c4312c27c826 ("drm/amdgpu: Cleanup 2 compiler warnings") > > > > > > Fixes tag > > > > > > Fixes: e4ae0fc drm/amdgpu: implement gfx8 post_soft_reset > > > > > > has these problem(s): > > > > > > - SHA1 should be at least 12 digits long > > > Can be fixed by setting core.abbrev to 12 (or more) or (for git v2.11 > > > or later) just making sure it is not set (or set to "auto"). > > > > > > Fixes tag > > > > > > Fixes: 5e01c09 drm/amdgpu/gfx_v8_0: Reorder the gfx, kiq and kcq rings > > > > > > has these problem(s): > > > > > > - Target SHA1 does not exist > > > > > > Maybe instead: > > > > > > Fixes: c6064de4b734 ("drm/amdgpu/gfx_v8_0: Reorder the gfx, kiq and kcq rings test sequence") > > > > Yeah the top 71 commits in the latest amdgpu pull got rebased, which > > is a bit much. Where are we with the "direct group commit, no more > > rebases" project for amd? Still stuck on CI troubles? > > In fairness, some of the rebasing was to squash in some bug fixes to > help with bisecting. As to direct commit, not enough internal > priority at the moment and too many other projects. I'll try to > double check them better going forward. Yeah I think internal prioritiy is probably not going to happen. The benefit imo is much more for everyone else, since it requires a more open&transparent process. E.g. for drm-intel a big reason for the public CI results is that we can make the committer model work for external people (which we do have). Hence my regular nags from me with my upstream community hat on, and AMD definitely can do this (viz radeonsi). Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch