From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: Keith Busch <keith.busch@intel.com>
Cc: <linux-kernel@vger.kernel.org>, <linux-acpi@vger.kernel.org>,
<linux-mm@kvack.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"Rafael Wysocki" <rafael@kernel.org>,
Dave Hansen <dave.hansen@intel.com>,
"Dan Williams" <dan.j.williams@intel.com>
Subject: Re: [PATCHv5 09/10] acpi/hmat: Register memory side cache attributes
Date: Wed, 6 Feb 2019 12:17:06 +0000 [thread overview]
Message-ID: <20190206121706.00005246@huawei.com> (raw)
In-Reply-To: <20190124230724.10022-10-keith.busch@intel.com>
On Thu, 24 Jan 2019 16:07:23 -0700
Keith Busch <keith.busch@intel.com> wrote:
> Register memory side cache attributes with the memory's node if HMAT
> provides the side cache iniformation table.
>
> Signed-off-by: Keith Busch <keith.busch@intel.com>
Trivial suggestion inline.
> ---
> drivers/acpi/hmat/hmat.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/drivers/acpi/hmat/hmat.c b/drivers/acpi/hmat/hmat.c
> index 917e6122b3f0..11f65b38e9f9 100644
> --- a/drivers/acpi/hmat/hmat.c
> +++ b/drivers/acpi/hmat/hmat.c
> @@ -245,6 +245,7 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header,
> const unsigned long end)
> {
> struct acpi_hmat_cache *cache = (void *)header;
> + struct node_cache_attrs cache_attrs;
> u32 attrs;
>
> if (cache->header.length < sizeof(*cache)) {
> @@ -258,6 +259,37 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header,
> cache->memory_PD, cache->cache_size, attrs,
> cache->number_of_SMBIOShandles);
>
> + cache_attrs.size = cache->cache_size;
> + cache_attrs.level = (attrs & ACPI_HMAT_CACHE_LEVEL) >> 4;
> + cache_attrs.line_size = (attrs & ACPI_HMAT_CACHE_LINE_SIZE) >> 16;
> +
> + switch ((attrs & ACPI_HMAT_CACHE_ASSOCIATIVITY) >> 8) {
FIELD_GET might be nice for these to avoid having the shifts and the mask.
> + case ACPI_HMAT_CA_DIRECT_MAPPED:
> + cache_attrs.associativity = NODE_CACHE_DIRECT_MAP;
> + break;
> + case ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING:
> + cache_attrs.associativity = NODE_CACHE_INDEXED;
> + break;
> + case ACPI_HMAT_CA_NONE:
> + default:
> + cache_attrs.associativity = NODE_CACHE_OTHER;
> + break;
> + }
> +
> + switch ((attrs & ACPI_HMAT_WRITE_POLICY) >> 12) {
> + case ACPI_HMAT_CP_WB:
> + cache_attrs.write_policy = NODE_CACHE_WRITE_BACK;
> + break;
> + case ACPI_HMAT_CP_WT:
> + cache_attrs.write_policy = NODE_CACHE_WRITE_THROUGH;
> + break;
> + case ACPI_HMAT_CP_NONE:
> + default:
> + cache_attrs.write_policy = NODE_CACHE_WRITE_OTHER;
> + break;
> + }
> +
> + node_add_cache(pxm_to_node(cache->memory_PD), &cache_attrs);
> return 0;
> }
>
next prev parent reply other threads:[~2019-02-06 12:17 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-24 23:07 [PATCHv5 00/10] Heterogeneuos memory node attributes Keith Busch
2019-01-24 23:07 ` [PATCHv5 01/10] acpi: Create subtable parsing infrastructure Keith Busch
2019-01-24 23:07 ` [PATCHv5 02/10] acpi: Add HMAT to generic parsing tables Keith Busch
2019-01-24 23:07 ` [PATCHv5 03/10] acpi/hmat: Parse and report heterogeneous memory Keith Busch
2019-02-05 12:12 ` Rafael J. Wysocki
2019-02-06 12:28 ` Jonathan Cameron
2019-02-06 16:06 ` Keith Busch
2019-02-06 16:39 ` Jonathan Cameron
2019-01-24 23:07 ` [PATCHv5 04/10] node: Link memory nodes to their compute nodes Keith Busch
2019-02-05 12:33 ` Rafael J. Wysocki
2019-02-05 14:48 ` Keith Busch
2019-02-05 14:52 ` Greg Kroah-Hartman
2019-02-05 15:17 ` Rafael J. Wysocki
2019-02-06 23:09 ` Keith Busch
2019-02-06 23:48 ` Rafael J. Wysocki
2019-02-06 12:26 ` Jonathan Cameron
2019-02-06 16:12 ` Keith Busch
2019-02-06 16:47 ` Jonathan Cameron
2019-02-07 11:35 ` Rafael J. Wysocki
2019-01-24 23:07 ` [PATCHv5 05/10] acpi/hmat: Register processor domain to its memory Keith Busch
2019-02-06 12:26 ` Jonathan Cameron
2019-01-24 23:07 ` [PATCHv5 06/10] node: Add heterogenous memory access attributes Keith Busch
2019-01-24 23:07 ` [PATCHv5 07/10] acpi/hmat: Register performance attributes Keith Busch
2019-02-06 12:24 ` Jonathan Cameron
2019-01-24 23:07 ` [PATCHv5 08/10] node: Add memory caching attributes Keith Busch
2019-02-06 12:24 ` Jonathan Cameron
2019-01-24 23:07 ` [PATCHv5 09/10] acpi/hmat: Register memory side cache attributes Keith Busch
2019-02-06 12:17 ` Jonathan Cameron [this message]
2019-01-24 23:07 ` [PATCHv5 10/10] doc/mm: New documentation for memory performance Keith Busch
2019-02-06 10:45 ` Jonathan Cameron
2019-02-06 16:25 ` Keith Busch
2019-01-28 14:00 ` [PATCHv5 00/10] Heterogeneuos memory node attributes Michal Hocko
2019-02-06 12:31 ` Jonathan Cameron
2019-02-06 17:19 ` Keith Busch
2019-02-06 17:30 ` Jonathan Cameron
2019-02-07 9:53 ` Jonathan Cameron
2019-02-07 15:08 ` Keith Busch
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190206121706.00005246@huawei.com \
--to=jonathan.cameron@huawei.com \
--cc=dan.j.williams@intel.com \
--cc=dave.hansen@intel.com \
--cc=gregkh@linuxfoundation.org \
--cc=keith.busch@intel.com \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mm@kvack.org \
--cc=rafael@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).