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From: Maxime Chevallier <maxime.chevallier@bootlin.com>
To: davem@davemloft.net
Cc: Maxime Chevallier <maxime.chevallier@bootlin.com>,
	netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
	Andrew Lunn <andrew@lunn.ch>,
	Florian Fainelli <f.fainelli@gmail.com>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	linux-arm-kernel@lists.infradead.org,
	Antoine Tenart <antoine.tenart@bootlin.com>,
	thomas.petazzoni@bootlin.com, gregory.clement@bootlin.com,
	miquel.raynal@bootlin.com, nadavh@marvell.com,
	stefanc@marvell.com, mw@semihalf.com
Subject: [PATCH net-next v2 01/10] net: phy: Update PHY linkmodes after config_init
Date: Thu,  7 Feb 2019 10:49:30 +0100	[thread overview]
Message-ID: <20190207094939.27369-2-maxime.chevallier@bootlin.com> (raw)
In-Reply-To: <20190207094939.27369-1-maxime.chevallier@bootlin.com>

We want to be able to update a PHY's supported list in the config_init
callback, so move the Pause parameters settings from phydrv->features
after calling config_init to make sure these  parameters aren't
overwritten.

Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
---
 drivers/net/phy/phy_device.c | 89 +++++++++++++++++++++++-------------
 1 file changed, 58 insertions(+), 31 deletions(-)

diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 891e0178b97f..18a10565efd4 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -1059,6 +1059,59 @@ static int phy_poll_reset(struct phy_device *phydev)
 	return 0;
 }
 
+/**
+ * phy_update_linkmodes - Update and sanitize linkmodes and pause parameters
+ * @phydev: The PHY device whose parameters we want to update.
+ *
+ * Description: The list of supported and advertised linkmodes is not
+ * straightforward to maintain, since PHYs and MACs are subject to quirks and
+ * erratas. This function re-builds the list of the supported pause parameters
+ * by taking into account the parameters expressed in the driver's features
+ * list.
+ */
+static void phy_update_linkmodes(struct phy_device *phydev)
+{
+	struct device_driver *drv = phydev->mdio.dev.driver;
+	struct phy_driver *phydrv = to_phy_driver(drv);
+
+	mutex_lock(&phydev->lock);
+
+	/* The Pause Frame bits indicate that the PHY can support passing
+	 * pause frames. During autonegotiation, the PHYs will determine if
+	 * they should allow pause frames to pass.  The MAC driver should then
+	 * use that result to determine whether to enable flow control via
+	 * pause frames.
+	 *
+	 * Normally, PHY drivers should not set the Pause bits, and instead
+	 * allow phylib to do that.  However, there may be some situations
+	 * (e.g. hardware erratum) where the driver wants to set only one
+	 * of these bits.
+	 */
+	if (test_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydrv->features) ||
+	    test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydrv->features)) {
+		linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+				   phydev->supported);
+		linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+				   phydev->supported);
+		if (test_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydrv->features))
+			linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+					 phydev->supported);
+		if (test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+			     phydrv->features))
+			linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+					 phydev->supported);
+	} else {
+		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+				 phydev->supported);
+		linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+				 phydev->supported);
+	}
+
+	linkmode_copy(phydev->advertising, phydev->supported);
+
+	mutex_unlock(&phydev->lock);
+}
+
 int phy_init_hw(struct phy_device *phydev)
 {
 	int ret = 0;
@@ -1082,6 +1135,11 @@ int phy_init_hw(struct phy_device *phydev)
 	if (phydev->drv->config_init)
 		ret = phydev->drv->config_init(phydev);
 
+	/* Update and sanitize the supported and advertised linkmodes, since
+	 * they might have been changed in config_init
+	 */
+	phy_update_linkmodes(phydev);
+
 	return ret;
 }
 EXPORT_SYMBOL(phy_init_hw);
@@ -2221,37 +2279,6 @@ static int phy_probe(struct device *dev)
 	 */
 	of_set_phy_eee_broken(phydev);
 
-	/* The Pause Frame bits indicate that the PHY can support passing
-	 * pause frames. During autonegotiation, the PHYs will determine if
-	 * they should allow pause frames to pass.  The MAC driver should then
-	 * use that result to determine whether to enable flow control via
-	 * pause frames.
-	 *
-	 * Normally, PHY drivers should not set the Pause bits, and instead
-	 * allow phylib to do that.  However, there may be some situations
-	 * (e.g. hardware erratum) where the driver wants to set only one
-	 * of these bits.
-	 */
-	if (test_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydrv->features) ||
-	    test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydrv->features)) {
-		linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
-				   phydev->supported);
-		linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
-				   phydev->supported);
-		if (test_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydrv->features))
-			linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
-					 phydev->supported);
-		if (test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
-			     phydrv->features))
-			linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
-					 phydev->supported);
-	} else {
-		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
-				 phydev->supported);
-		linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
-				 phydev->supported);
-	}
-
 	/* Set the state to READY by default */
 	phydev->state = PHY_READY;
 
-- 
2.19.2


  reply	other threads:[~2019-02-07  9:50 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-07  9:49 [PATCH net-next v2 00/10] net: phy: Add support for 2.5GBASET PHYs Maxime Chevallier
2019-02-07  9:49 ` Maxime Chevallier [this message]
2019-02-07 10:31   ` [PATCH net-next v2 01/10] net: phy: Update PHY linkmodes after config_init Maxime Chevallier
2019-02-07 13:48   ` Andrew Lunn
2019-02-07 13:55     ` Maxime Chevallier
2019-02-07 18:21       ` Heiner Kallweit
2019-02-07  9:49 ` [PATCH net-next v2 02/10] net: phy: Mask-out non-compatible modes when setting the max-speed Maxime Chevallier
2019-02-07 13:59   ` Andrew Lunn
2019-02-07  9:49 ` [PATCH net-next v2 03/10] net: phy: Move of_set_phy_eee_broken to phy-core.c Maxime Chevallier
2019-02-07 14:01   ` Andrew Lunn
2019-02-07  9:49 ` [PATCH net-next v2 04/10] net: phy: Automatically fill the generic TP, FIBRE and Backplane modes Maxime Chevallier
2019-02-07 14:09   ` Andrew Lunn
2019-02-07 14:49     ` Maxime Chevallier
2019-02-07  9:49 ` [PATCH net-next v2 05/10] net: phy: Extract genphy_c45_pma_read_abilities from marvell10g Maxime Chevallier
2019-02-07  9:49 ` [PATCH net-next v2 06/10] net: phy: Add generic support for 2.5GBaseT and 5GBaseT Maxime Chevallier
2019-02-07  9:49 ` [PATCH net-next v2 07/10] net: phy: marvell10g: Add support for 2.5GBASET Maxime Chevallier
2019-02-07 14:15   ` Andrew Lunn
2019-02-07 23:48   ` Russell King - ARM Linux admin
2019-02-20 10:54     ` Maxime Chevallier
2019-02-07  9:49 ` [PATCH net-next v2 08/10] net: phy: marvell10g: Force reading of 2.5/5G Maxime Chevallier
2019-02-07  9:49 ` [PATCH net-next v2 09/10] net: mvpp2: Add 2.5GBaseT support Maxime Chevallier
2019-02-07 14:17   ` Andrew Lunn
2019-02-07  9:49 ` [PATCH net-next v2 10/10] net: phy: marvell10g: add support for the 88x2110 PHY Maxime Chevallier
2019-02-09 13:22 ` [PATCH net-next v2 00/10] net: phy: Add support for 2.5GBASET PHYs Heiner Kallweit
2019-02-09 16:25   ` Andrew Lunn
2019-02-09 16:28     ` Heiner Kallweit
2019-02-11  7:46   ` Maxime Chevallier

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