From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7100FC282CE for ; Mon, 11 Feb 2019 14:57:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3EEEB2229E for ; Mon, 11 Feb 2019 14:57:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1549897056; bh=jG2CxJDQgrw3pDzq+PiqJq4pFDtneuyjLkztUQv2Tjs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=hFkXxz10LBpL9+u9ejo+sXajFPoOf1XsN+A7GjeLqlyc5fGEsxslRCJ1L56FvoP/E GYjJqrSgOj+vYcJ8RJu0+OW+NBLKZkT/ffCmXh5Mbw/06K7yxY6B2+hTIyXH1rOU1q 2/xvfKQEQdpQU/V12h9pm7IThvT0D2haSkekKlMw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389380AbfBKO5e (ORCPT ); Mon, 11 Feb 2019 09:57:34 -0500 Received: from mail.kernel.org ([198.145.29.99]:44942 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389365AbfBKO5b (ORCPT ); Mon, 11 Feb 2019 09:57:31 -0500 Received: from localhost (5356596B.cm-6-7b.dynamic.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 310B92229E; Mon, 11 Feb 2019 14:57:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1549897050; bh=jG2CxJDQgrw3pDzq+PiqJq4pFDtneuyjLkztUQv2Tjs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jKCjcb9wXWhogdjiO6e8N5l8Ne+ECH78Aivvet9Eh9rVxikffpW1igT3PBcovVx0c 5smuhHajaKD9Utc7H2aC9sSdu5sT7/wQUHyI8QE44hBS/arSs+ELnxE6ISUC5+9G1P fsxHte8azrU/l31lSgreUW5NesyxbDuZXrrAAr20= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Markos Chandras , Paul Burton , linux-mips@vger.kernel.org, Jakub Kicinski , Song Liu , Jiong Wang , Alexei Starovoitov , Sasha Levin Subject: [PATCH 4.14 074/205] mips: bpf: fix encoding bug for mm_srlv32_op Date: Mon, 11 Feb 2019 15:17:52 +0100 Message-Id: <20190211141833.560166932@linuxfoundation.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190211141827.214852402@linuxfoundation.org> References: <20190211141827.214852402@linuxfoundation.org> User-Agent: quilt/0.65 X-stable: review X-Patchwork-Hint: ignore MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 4.14-stable review patch. If anyone has any objections, please let me know. ------------------ [ Upstream commit 17f6c83fb5ebf7db4fcc94a5be4c22d5a7bfe428 ] For micro-mips, srlv inside POOL32A encoding space should use 0x50 sub-opcode, NOT 0x90. Some early version ISA doc describes the encoding as 0x90 for both srlv and srav, this looks to me was a typo. I checked Binutils libopcode implementation which is using 0x50 for srlv and 0x90 for srav. v1->v2: - Keep mm_srlv32_op sorted by value. Fixes: f31318fdf324 ("MIPS: uasm: Add srlv uasm instruction") Cc: Markos Chandras Cc: Paul Burton Cc: linux-mips@vger.kernel.org Acked-by: Jakub Kicinski Acked-by: Song Liu Signed-off-by: Jiong Wang Signed-off-by: Alexei Starovoitov Signed-off-by: Sasha Levin --- arch/mips/include/uapi/asm/inst.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h index c05dcf5ab414..273ef58f4d43 100644 --- a/arch/mips/include/uapi/asm/inst.h +++ b/arch/mips/include/uapi/asm/inst.h @@ -369,8 +369,8 @@ enum mm_32a_minor_op { mm_ext_op = 0x02c, mm_pool32axf_op = 0x03c, mm_srl32_op = 0x040, + mm_srlv32_op = 0x050, mm_sra_op = 0x080, - mm_srlv32_op = 0x090, mm_rotr_op = 0x0c0, mm_lwxs_op = 0x118, mm_addu32_op = 0x150, -- 2.19.1