From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIMWL_WL_MED,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 117B3C43381 for ; Thu, 14 Feb 2019 14:56:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D392E2229F for ; Thu, 14 Feb 2019 14:56:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=bgdev-pl.20150623.gappssmtp.com header.i=@bgdev-pl.20150623.gappssmtp.com header.b="BqkA7cFg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392124AbfBNO4Y (ORCPT ); Thu, 14 Feb 2019 09:56:24 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:42874 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2439446AbfBNOwr (ORCPT ); Thu, 14 Feb 2019 09:52:47 -0500 Received: by mail-wr1-f65.google.com with SMTP id q18so6768283wrx.9 for ; Thu, 14 Feb 2019 06:52:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M5s8LgF6tZAAsjgatoDHdRTjLQOzD7FAKkqTEC3Dngk=; b=BqkA7cFgY5eQZK7myk8BKxWfGkvj9AutRjzEtoyt1z8IetYbkItoh3f7UuvdeqD6K1 sVr784C5j3xCUGprBkB/fQ0iANsaCu/UTxfxE8x8TWP3NYX2PD62Z+IODyAYNYPxK9Dj lqyAwEVKi8jJyOm3JY2uQcl2Yw79QGcJ9IV82PLhySB74KpqPhJJGXHIVHMlrL+UTwvq PHEPHkDaGcO9TQudMMs+RBi3kqhjnmfV5bKV+YCiyhT7xLu5FPAJHmFZ68eIYBbccpm4 IRnUQAPN8WH36JIw6g5eFxBS73Q2quU6joKwBAQIsIqv4+n2YLg9dz4S7JgsiR3Dv3lD K8Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M5s8LgF6tZAAsjgatoDHdRTjLQOzD7FAKkqTEC3Dngk=; b=G5K6b/7lYdRmRq/FmpMjbv5rkX+JjqrYM1dz2buJ9ONG03jSpWaYhj8TShzTRy820W qBrH1sp/Xu/9psrKvCOXR7NTtSfc0qfjIufu+BCV98EhBWD+mUvjnE5UKflWeGGSCztC sCEtssm+xTJSL88w4uuc21ObzbUeUCuFB2CWZc4y44DTHAfXXPaLC59opVLwMV4nYm5L ZFNsYVIeO1ZoVMqCYVE5bIYr1JVdo/bIB8F6LfkjU9gQu7fHig4m8B2a++7ZE6RtbkbI mM3ok6Dk9ynzsAth25OJ7jjEHlLgkOQw5xSwlKB2Shj0ShAhdJFCgwXudT+n1cNL04ec ygFw== X-Gm-Message-State: AHQUAuZtWz0FPm5i7sLWUQb/W6kxcAo7Da5PNXi3P8fVr7Hk0LUDa3OD Qx4crY36iaoUAN4LhQjBNiUM1A== X-Google-Smtp-Source: AHgI3Ibl8067TtcXcDLRsWxeFZGUOkyzXVfDDfiNstZzj6kRDNEVTg3BvvFO9JxCuRx3meXDC2CJ/Q== X-Received: by 2002:adf:dfca:: with SMTP id q10mr3265081wrn.45.1550155965831; Thu, 14 Feb 2019 06:52:45 -0800 (PST) Received: from debian-brgl.home ([2a01:cb1d:af:5b00:6d6c:8493:1ab5:dad7]) by smtp.gmail.com with ESMTPSA id y20sm4181005wra.51.2019.02.14.06.52.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 06:52:45 -0800 (PST) From: Bartosz Golaszewski To: Dmitry Torokhov , Sekhar Nori , Kevin Hilman , Thomas Gleixner , Jason Cooper , Marc Zyngier , David Lechner Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v4 03/37] ARM: davinci: aintc: use irq domain Date: Thu, 14 Feb 2019 15:51:57 +0100 Message-Id: <20190214145231.8750-4-brgl@bgdev.pl> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214145231.8750-1-brgl@bgdev.pl> References: <20190214145231.8750-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Bartosz Golaszewski We need to create an irq domain if we want to select SPARSE_IRQ. The cp-intc driver already supports it, but aintc doesn't. Use the helpers provided by the generic irq chip abstraction. Signed-off-by: Bartosz Golaszewski --- arch/arm/mach-davinci/irq.c | 35 +++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index 952dc126c390..efba6dbdfd62 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -40,23 +41,23 @@ #define IRQ_INTPRI0_REG_OFFSET 0x0030 #define IRQ_INTPRI7_REG_OFFSET 0x004C +static struct irq_domain *davinci_irq_domain; + static inline void davinci_irq_writel(unsigned long value, int offset) { __raw_writel(value, davinci_intc_base + offset); } static __init void -davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) +davinci_irq_setup_gc(void __iomem *base, + unsigned int irq_start, unsigned int num) { struct irq_chip_generic *gc; struct irq_chip_type *ct; - gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq); - if (!gc) { - pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n", - __func__, irq_start); - return; - } + gc = irq_get_domain_generic_chip(davinci_irq_domain, irq_start); + gc->reg_base = base; + gc->irq_base = irq_start; ct = gc->chip_types; ct->chip.irq_ack = irq_gc_ack_set_bit; @@ -74,6 +75,7 @@ void __init davinci_irq_init(void) { unsigned i, j; const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios; + int ret, irq_base; davinci_intc_type = DAVINCI_INTC_TYPE_AINTC; davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K); @@ -110,8 +112,25 @@ void __init davinci_irq_init(void) davinci_irq_writel(pri, i); } + irq_base = irq_alloc_descs(-1, 0, davinci_soc_info.intc_irq_num, 0); + if (WARN_ON(irq_base < 0)) + return; + + davinci_irq_domain = irq_domain_add_legacy(NULL, + davinci_soc_info.intc_irq_num, + irq_base, 0, &irq_domain_simple_ops, + NULL); + if (WARN_ON(!davinci_irq_domain)) + return; + + ret = irq_alloc_domain_generic_chips(davinci_irq_domain, 32, 1, + "AINTC", handle_edge_irq, + IRQ_NOREQUEST | IRQ_NOPROBE, 0, 0); + if (WARN_ON(ret)) + return; + for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04) - davinci_alloc_gc(davinci_intc_base + j, i, 32); + davinci_irq_setup_gc(davinci_intc_base + j, irq_base + i, 32); irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq); } -- 2.20.1