* [PATCH v4 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical
@ 2019-02-14 16:32 matthias.bgg
2019-02-26 17:55 ` Stephen Boyd
0 siblings, 1 reply; 3+ messages in thread
From: matthias.bgg @ 2019-02-14 16:32 UTC (permalink / raw)
To: mturquette, sboyd, kevin-cw.chen, mars.cheng
Cc: sean.wang, matthias.bgg, jasu, linux-clk, linux-kernel,
linux-arm-kernel, linux-mediatek
From: Jasper Mattsson <jasu@njomotys.info>
Currently, DRAM-related clocks are not marked with CLK_IS_CRITICAL
for MT6797. This causes memory corruption when the system is
booted without clk_ignore_unused.
This patch marks MUX ddrphycfg_sel as well as gates infra_dramc_f26m
and infra_dramc_b_f26m as CLK_IS_CRITICAL.
Signed-off-by: Jasper Mattsson <jasu@njomotys.info>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
drivers/clk/mediatek/clk-mt6797.c | 68 +++++++++++++++++++------------
1 file changed, 43 insertions(+), 25 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c
index 5702bc974ed9..c2b46b184b9a 100644
--- a/drivers/clk/mediatek/clk-mt6797.c
+++ b/drivers/clk/mediatek/clk-mt6797.c
@@ -324,6 +324,10 @@ static const char * const anc_md32_parents[] = {
"univpll_d5",
};
+/*
+ * Clock mux ddrphycfg is needed by the DRAM controller. We mark it as
+ * critical as otherwise the system will hang after boot.
+ */
static const struct mtk_composite top_muxes[] = {
MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre",
ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1),
@@ -331,8 +335,8 @@ static const struct mtk_composite top_muxes[] = {
ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
0x0040, 0, 2),
- MUX(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
- 0x0040, 16, 2),
+ MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
+ 0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
0x0040, 24, 2),
MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
@@ -424,33 +428,45 @@ static const struct mtk_gate_regs infra2_cg_regs = {
.sta_ofs = 0x00b0,
};
-#define GATE_ICG0(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = &infra0_cg_regs, \
- .shift = _shift, \
- .ops = &mtk_clk_gate_ops_setclr, \
+#define GATE_ICG0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
}
-#define GATE_ICG1(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = &infra1_cg_regs, \
- .shift = _shift, \
- .ops = &mtk_clk_gate_ops_setclr, \
+#define GATE_ICG1(_id, _name, _parent, _shift) \
+ GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ .flags = _flags, \
}
-#define GATE_ICG2(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = &infra2_cg_regs, \
- .shift = _shift, \
- .ops = &mtk_clk_gate_ops_setclr, \
+#define GATE_ICG2(_id, _name, _parent, _shift) \
+ GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ .flags = _flags, \
}
+/*
+ * Clock gates dramc and dramc_b are needed by the DRAM controller.
+ * We mark them as critical as otherwise the system will hang after boot.
+ */
static const struct mtk_gate infra_clks[] = {
GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0),
GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1),
@@ -505,7 +521,8 @@ static const struct mtk_gate infra_clks[] = {
GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
- GATE_ICG1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
+ GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
+ "clk26m", 31, CLK_IS_CRITICAL),
GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
@@ -516,7 +533,8 @@ static const struct mtk_gate infra_clks[] = {
GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
- GATE_ICG2(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m", "clk26m", 11),
+ GATE_ICG2_FLAGS(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m",
+ "clk26m", 11, CLK_IS_CRITICAL),
GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),
--
2.20.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v4 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical
2019-02-14 16:32 [PATCH v4 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical matthias.bgg
@ 2019-02-26 17:55 ` Stephen Boyd
2019-02-27 10:36 ` Mars Cheng
0 siblings, 1 reply; 3+ messages in thread
From: Stephen Boyd @ 2019-02-26 17:55 UTC (permalink / raw)
To: kevin-cw.chen, mars.cheng, matthias.bgg, mturquette
Cc: sean.wang, matthias.bgg, jasu, linux-clk, linux-kernel,
linux-arm-kernel, linux-mediatek
Quoting matthias.bgg@kernel.org (2019-02-14 08:32:42)
> From: Jasper Mattsson <jasu@njomotys.info>
>
> Currently, DRAM-related clocks are not marked with CLK_IS_CRITICAL
> for MT6797. This causes memory corruption when the system is
> booted without clk_ignore_unused.
> This patch marks MUX ddrphycfg_sel as well as gates infra_dramc_f26m
> and infra_dramc_b_f26m as CLK_IS_CRITICAL.
>
> Signed-off-by: Jasper Mattsson <jasu@njomotys.info>
> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
Applied to clk-next
Would be nice to get someone from mediatek to ack it, but I can't wait
forever.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v4 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical
2019-02-26 17:55 ` Stephen Boyd
@ 2019-02-27 10:36 ` Mars Cheng
0 siblings, 0 replies; 3+ messages in thread
From: Mars Cheng @ 2019-02-27 10:36 UTC (permalink / raw)
To: Stephen Boyd
Cc: kevin-cw.chen, matthias.bgg, mturquette, sean.wang, linux-kernel,
jasu, matthias.bgg, linux-mediatek, linux-clk, linux-arm-kernel
Hi Stephen
On Tue, 2019-02-26 at 09:55 -0800, Stephen Boyd wrote:
> Quoting matthias.bgg@kernel.org (2019-02-14 08:32:42)
> > From: Jasper Mattsson <jasu@njomotys.info>
> >
> > Currently, DRAM-related clocks are not marked with CLK_IS_CRITICAL
> > for MT6797. This causes memory corruption when the system is
> > booted without clk_ignore_unused.
> > This patch marks MUX ddrphycfg_sel as well as gates infra_dramc_f26m
> > and infra_dramc_b_f26m as CLK_IS_CRITICAL.
> >
> > Signed-off-by: Jasper Mattsson <jasu@njomotys.info>
> > Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
> > ---
>
> Applied to clk-next
>
> Would be nice to get someone from mediatek to ack it, but I can't wait
> forever.
Acked-by:Mars Cheng <mars.cheng@mediatek.com>
Thanks a lot.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-02-14 16:32 [PATCH v4 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical matthias.bgg
2019-02-26 17:55 ` Stephen Boyd
2019-02-27 10:36 ` Mars Cheng
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