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Thu, 28 Feb 2019 15:36:11 +0000 From: "Ghannam, Yazen" To: "linux-edac@vger.kernel.org" CC: "Ghannam, Yazen" , "linux-kernel@vger.kernel.org" , "bp@alien8.de" Subject: [PATCH v3 2/6] EDAC/amd64: Use a macro for iterating over Unified Memory Controllers Thread-Topic: [PATCH v3 2/6] EDAC/amd64: Use a macro for iterating over Unified Memory Controllers Thread-Index: AQHUz3tUVSmGHbJk/EizNTHby3+Ohw== Date: Thu, 28 Feb 2019 15:36:10 +0000 Message-ID: <20190228153558.127292-2-Yazen.Ghannam@amd.com> References: <20190228153558.127292-1-Yazen.Ghannam@amd.com> In-Reply-To: <20190228153558.127292-1-Yazen.Ghannam@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN6PR06CA0028.namprd06.prod.outlook.com (2603:10b6:805:8e::41) To SN6PR12MB2639.namprd12.prod.outlook.com (2603:10b6:805:6f::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Yazen.Ghannam@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.77.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e9aae43c-ec18-4549-f6f5-08d69d9276b7 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(4618075)(2017052603328)(7153060)(7193020);SRVR:SN6PR12MB2765; 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received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: FIUZQWSRSvkCYXQE1GOIFgmp1fuKYxS78bvD00yvwMIy6zukT1prVuEU2XObwpnQXOLi2m++r1v3R5O7r8Y+/4u+zEXuqB9nr3Jp/x+lkg1HhGP9DYo3CB33xz4v+wMP6aEllpzxW0QuGqU93o33ivFQEV3fUqBPEj49O7ht0B6Fx9bI4Iv97sLu3y2V60yZwJUrm8RhBdMasrWRE0UPf94BMsqsaInD4L6qfmhYkEimIJ0vkQjI2rl2YOlpnUXENQiNAWSfoMftO9ulPwjKMx/N4nsF6SkLRIEsfxncxJ5YzadKmGYkGYx0Ug6jPJeQNwSgOlXScMaWTQVhZbWMK2PWZ7YM8maIbfTw0Zo1S5BzMCk9mBSNjpAkDkqxaV3tr5Ki+79LDO8VXUc/lmV2CvN8VKT2pt6tHJxNiLzAxb8= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: e9aae43c-ec18-4549-f6f5-08d69d9276b7 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Feb 2019 15:36:10.4639 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2765 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yazen Ghannam Define and use a macro for looping over the number of Unified Memory Controllers. No functional change. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20190226172532.12924-3-Yazen.Ghannam@amd.com v2->v3: * Apply V2 Patch 3 before V2 Patch 2. v1->v2: * New in V2. Please see comment on Patch 2 V1 at link above. drivers/edac/amd64_edac.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 98e8da9d9f5b..e4fd459d807a 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -449,6 +449,9 @@ static void get_cs_base_and_mask(struct amd64_pvt *pvt,= int csrow, u8 dct, #define for_each_chip_select_mask(i, dct, pvt) \ for (i =3D 0; i < pvt->csels[dct].m_cnt; i++) =20 +#define for_each_umc(i) \ + for (i =3D 0; i < NUM_UMCS; i++) + /* * @input_addr is an InputAddr associated with the node given by mci. Retu= rn the * csrow that input_addr maps to, or -1 on failure (no csrow claims input_= addr). @@ -722,7 +725,7 @@ static unsigned long determine_edac_cap(struct amd64_pv= t *pvt) if (pvt->umc) { u8 i, umc_en_mask =3D 0, dimm_ecc_en_mask =3D 0; =20 - for (i =3D 0; i < NUM_UMCS; i++) { + for_each_umc(i) { if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) continue; =20 @@ -811,7 +814,7 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt) struct amd64_umc *umc; u32 i, tmp, umc_base; =20 - for (i =3D 0; i < NUM_UMCS; i++) { + for_each_umc(i) { umc_base =3D get_umc_base(i); umc =3D &pvt->umc[i]; =20 @@ -1388,7 +1391,7 @@ static int f17_early_channel_count(struct amd64_pvt *= pvt) int i, channels =3D 0; =20 /* SDP Control bit 31 (SdpInit) is clear for unused UMC channels */ - for (i =3D 0; i < NUM_UMCS; i++) + for_each_umc(i) channels +=3D !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT); =20 amd64_info("MCT channel count: %d\n", channels); @@ -2612,7 +2615,7 @@ static void determine_ecc_sym_sz(struct amd64_pvt *pv= t) if (pvt->umc) { u8 i; =20 - for (i =3D 0; i < NUM_UMCS; i++) { + for_each_umc(i) { /* Check enabled channels only: */ if ((pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) && (pvt->umc[i].ecc_ctrl & BIT(7))) { @@ -2648,7 +2651,7 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt) u32 i, umc_base; =20 /* Read registers from each UMC */ - for (i =3D 0; i < NUM_UMCS; i++) { + for_each_umc(i) { =20 umc_base =3D get_umc_base(i); umc =3D &pvt->umc[i]; @@ -3061,7 +3064,7 @@ static bool ecc_enabled(struct pci_dev *F3, u16 nid) if (boot_cpu_data.x86 >=3D 0x17) { u8 umc_en_mask =3D 0, ecc_en_mask =3D 0; =20 - for (i =3D 0; i < NUM_UMCS; i++) { + for_each_umc(i) { u32 base =3D get_umc_base(i); =20 /* Only check enabled UMCs. */ @@ -3114,7 +3117,7 @@ f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci,= struct amd64_pvt *pvt) { u8 i, ecc_en =3D 1, cpk_en =3D 1; =20 - for (i =3D 0; i < NUM_UMCS; i++) { + for_each_umc(i) { if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { ecc_en &=3D !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED); cpk_en &=3D !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP); --=20 2.17.1