From: Catalin Marinas <catalin.marinas@arm.com>
To: James Morse <james.morse@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Mark Rutland <mark.rutland@arm.com>,
Will Deacon <will.deacon@arm.com>,
Zhang Lei <zhang.lei@jp.fujitsu.com>
Subject: Re: [PATCH v5] arm64: Add workaround for Fujitsu A64FX erratum 010001
Date: Thu, 28 Feb 2019 17:15:07 +0000 [thread overview]
Message-ID: <20190228171506.GC226495@arrakis.emea.arm.com> (raw)
In-Reply-To: <20190226184341.26083-1-james.morse@arm.com>
On Tue, Feb 26, 2019 at 06:43:41PM +0000, James Morse wrote:
> From: Zhang Lei <zhang.lei@jp.fujitsu.com>
>
> On the Fujitsu-A64FX cores ver(1.0, 1.1), memory access may cause
> an undefined fault (Data abort, DFSC=0b111111). This fault occurs under
> a specific hardware condition when a load/store instruction performs an
> address translation. Any load/store instruction, except non-fault access
> including Armv8 and SVE might cause this undefined fault.
>
> The TCR_ELx.NFD1 bit is used by the kernel when CONFIG_RANDOMIZE_BASE
> is enabled to mitigate timing attacks against KASLR where the kernel
> address space could be probed using the FFR and suppressed fault on
> SVE loads.
>
> Since this erratum causes spurious exceptions, which may corrupt
> the exception registers, we clear the TCR_ELx.NFDx=1 bits when
> booting on an affected CPU.
>
> Signed-off-by: Zhang Lei <zhang.lei@jp.fujitsu.com>
> [Generated MIDR value/mask for __cpu_setup(), removed spurious-fault handler
> and always disabled the NFDx bits on affected CPUs]
> Signed-off-by: James Morse <james.morse@arm.com>
> Tested-by: zhang.lei <zhang.lei@jp.fujitsu.com>
Queued for 5.1. Thanks.
--
Catalin
prev parent reply other threads:[~2019-02-28 17:15 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-26 18:43 [PATCH v5] arm64: Add workaround for Fujitsu A64FX erratum 010001 James Morse
2019-02-28 17:15 ` Catalin Marinas [this message]
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