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Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv4 21/28] PCI: mobiveil: add Byte and Half-Word width register accessors Thread-Topic: [PATCHv4 21/28] PCI: mobiveil: add Byte and Half-Word width register accessors Thread-Index: AQHU1+1kIDVQdssEHU+uhZ59DBwaQA== Date: Mon, 11 Mar 2019 09:32:49 +0000 Message-ID: <20190311093130.7209-22-Zhiqiang.Hou@nxp.com> References: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK0PR03CA0015.apcprd03.prod.outlook.com (2603:1096:203:2e::27) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:ad::19) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: dbad3283-6072-4fc0-2edb-08d6a604869a x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600127)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020);SRVR:AM6PR04MB4168; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: PJjDrI+/iyZcLkljKuiiwNRWftZpASGNQsArgOlAFiglwYg6SWaDnKSHHdqmlCmmlM1Iw/nHGtQZhSeBEwX+tAW0LL1b32ecC6jkAKz/ikTAqLtMBFX4LB18fMgwp7+sc06rD+iYJmdmQS9nG82eOWfyBfqKvK6HJzcAQd0eaezHIrw/uifE/Fs4I+iiltJuZiMgdt8s8wQ3AsVWtfoCrboM2o4wseBFUtHow+prsuBoibppNcBoGuiyZck+RjCVABUo0ljpXgcmu8U8qWs3VjHf5un7SNXHsn0+MvkDfm7kJ8/kW4dEcWJ63dNEO6TOSNE0LVG+dqWwfVgmPt1S5sYrcqcutyrY5NDDBd35SfcA3zva44iVC2K6njFp3ceOzF9zcElskC/HHLS0CN4rwFbhcDrs+4W3OWsz4ARnmcU= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: dbad3283-6072-4fc0-2edb-08d6a604869a X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Mar 2019 09:32:49.0857 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4168 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Hou Zhiqiang As there are some Byte and Half-Work width registers in PCIe configuration space, add Byte and Half-Word width register accessors. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian Reviewed-by: Subrahmanya Lingappa --- V4: - no change .../pci/controller/mobiveil/pcie-mobiveil.h | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/= controller/mobiveil/pcie-mobiveil.h index 81685840b378..933c2f34bc52 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -181,9 +181,29 @@ static inline u32 csr_readl(struct mobiveil_pcie *pcie= , u32 off) return csr_read(pcie, off, 0x4); } =20 +static inline u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) +{ + return csr_read(pcie, off, 0x2); +} + +static inline u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) +{ + return csr_read(pcie, off, 0x1); +} + static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off= ) { csr_write(pcie, val, off, 0x4); } =20 +static inline void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off= ) +{ + csr_write(pcie, val, off, 0x2); +} + +static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off= ) +{ + csr_write(pcie, val, off, 0x1); +} + #endif /* _PCIE_MOBIVEIL_H */ --=20 2.17.1