* [PATCH] clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
@ 2019-03-14 11:21 Icenowy Zheng
2019-03-14 15:46 ` Maxime Ripard
0 siblings, 1 reply; 2+ messages in thread
From: Icenowy Zheng @ 2019-03-14 11:21 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-sunxi, Icenowy Zheng
The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8.
Fix this problem.
Fixes: 0380126eb9af ("clk: sunxi-ng: add support for suniv F1C100s SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
index a09dfbe36402..dc9f0a365664 100644
--- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
+++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
@@ -240,7 +240,7 @@ static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
- 0x0cc, BIT(8), 0);
+ 0x0cc, BIT(1), 0);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
0x100, BIT(0), 0);
--
2.18.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
2019-03-14 11:21 [PATCH] clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset Icenowy Zheng
@ 2019-03-14 15:46 ` Maxime Ripard
0 siblings, 0 replies; 2+ messages in thread
From: Maxime Ripard @ 2019-03-14 15:46 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Chen-Yu Tsai, linux-arm-kernel, linux-clk, linux-kernel, linux-sunxi
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On Thu, Mar 14, 2019 at 07:21:08PM +0800, Icenowy Zheng wrote:
> The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8.
>
> Fix this problem.
>
> Fixes: 0380126eb9af ("clk: sunxi-ng: add support for suniv F1C100s SoC")
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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