From: Maxime Ripard <maxime.ripard@bootlin.com>
To: Icenowy Zheng <icenowy@aosc.io>
Cc: Chen-Yu Tsai <wens@csie.org>,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: Re: [PATCH] clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
Date: Thu, 14 Mar 2019 16:46:28 +0100 [thread overview]
Message-ID: <20190314154627.7f322sd2sd7asnnc@flea> (raw)
In-Reply-To: <20190314112108.6150-1-icenowy@aosc.io>
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On Thu, Mar 14, 2019 at 07:21:08PM +0800, Icenowy Zheng wrote:
> The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8.
>
> Fix this problem.
>
> Fixes: 0380126eb9af ("clk: sunxi-ng: add support for suniv F1C100s SoC")
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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prev parent reply other threads:[~2019-03-14 15:46 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-14 11:21 [PATCH] clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset Icenowy Zheng
2019-03-14 15:46 ` Maxime Ripard [this message]
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