[PATCH v3 1/3] x86/MCE: Add function to allow filtering of MCA errors

[PATCH v3 1/3] x86/MCE: Add function to allow filtering of MCA errors

[Ghannam, Yazen]

From: Yazen Ghannam <yazen.ghannam@amd.com>

Some systems may report spurious MCA errors. In general, spurious MCA
errors may be disabled by clearing a particular bit in MCA_CTL. However,
clearing a bit in MCA_CTL may not be recommended for some errors, so the
only option is to ignore them.

An MCA error is printed and handled after it has been added to the MCE
event pool. So an MCA error can be ignored by not adding it to the pool.

Define a default function that does not filter any errors.

Check if an MCA error should be filtered out when adding it to the MCE
event pool.

Cc: <stable@vger.kernel.org> # 4.14.x
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20190321202505.5553-1-Yazen.Ghannam@amd.com

v2->v3:
* Define a regular function rather than function pointer.
* Update comment in header file.

v1->v2:
* This is a new patch replacing V1 Patch 1 which is no longer needed.

 arch/x86/include/asm/mce.h        | 3 +++
 arch/x86/kernel/cpu/mce/core.c    | 5 +++++
 arch/x86/kernel/cpu/mce/genpool.c | 3 +++
 3 files changed, 11 insertions(+)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 22d05e3835f0..ec5bf1cad217 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -253,6 +253,9 @@ extern void mce_disable_bank(int bank);
 extern void (*machine_check_vector)(struct pt_regs *, long error_code);
 void do_machine_check(struct pt_regs *, long);
 
+/* Decide whether to add MCE record to MCE event pool or filter it out. */
+extern bool filter_mce(struct mce *m);
+
 /*
  * Threshold handler
  */
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index b7fb541a4873..12d61b8f8154 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1771,6 +1771,11 @@ static void __mcheck_cpu_init_timer(void)
 	mce_start_timer(t);
 }
 
+bool filter_mce(struct mce *m)
+{
+	return false;
+}
+
 /* Handle unconfigured int18 (should never happen) */
 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
 {
diff --git a/arch/x86/kernel/cpu/mce/genpool.c b/arch/x86/kernel/cpu/mce/genpool.c
index 3395549c51d3..64d1d5a00f39 100644
--- a/arch/x86/kernel/cpu/mce/genpool.c
+++ b/arch/x86/kernel/cpu/mce/genpool.c
@@ -99,6 +99,9 @@ int mce_gen_pool_add(struct mce *mce)
 {
 	struct mce_evt_llist *node;
 
+	if (filter_mce(mce))
+		return -EINVAL;
+
 	if (!mce_evt_pool)
 		return -EINVAL;
 
-- 
2.17.1

[PATCH v3 2/3] x86/MCE/AMD: Don't report L1 BTB MCA errors on some Family 17h models

[Ghannam, Yazen]

From: Yazen Ghannam <yazen.ghannam@amd.com>

AMD Family 17h Models 10h-2Fh may report a high number of L1 BTB MCA
errors under certain conditions. The errors are benign and can safely be
ignored. However, the high error rate may cause the MCA threshold
counter to overflow causing a high rate of thresholding interrupts. In
addition, users may see the errors reported through the AMD MCE decoder
module, even with the interrupt disabled, due to MCA polling.

This error is reported through the Instruction Fetch bank.

Clear the "Counter Present" bit in the Instruction Fetch bank's
MCA_MISC0 register. This will prevent enabling MCA thresholding on this
bank which will prevent the high interrupt rate due to this error.

Define an AMD-specific function to filter these errors from the MCE
event pool.

Cc: <stable@vger.kernel.org> # 4.14.x: c95b323dcd35: x86/MCE/AMD: Turn off MC4_MISC thresholding on all family 0x15 models
Cc: <stable@vger.kernel.org> # 4.14.x: 30aa3d26edb0: x86/MCE/AMD: Carve out the MC4_MISC thresholding quirk
Cc: <stable@vger.kernel.org> # 4.14.x
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20190321202505.5553-2-Yazen.Ghannam@amd.com

v2->v3:
* Define a simple AMD-specific filter function rather than a
  model-specific one.

v1->v2:
* Filter out the error earlier in MCE code rather than later in EDAC.

 arch/x86/include/asm/mce.h     |  2 ++
 arch/x86/kernel/cpu/mce/amd.c  | 54 ++++++++++++++++++++++++++--------
 arch/x86/kernel/cpu/mce/core.c |  3 ++
 3 files changed, 47 insertions(+), 12 deletions(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index ec5bf1cad217..50f76a7956cc 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -344,6 +344,7 @@ extern struct smca_bank smca_banks[MAX_NR_BANKS];
 
 extern const char *smca_get_long_name(enum smca_bank_types t);
 extern bool amd_mce_is_memory_error(struct mce *m);
+extern bool filter_mce_amd(struct mce *m);
 
 extern int mce_threshold_create_device(unsigned int cpu);
 extern int mce_threshold_remove_device(unsigned int cpu);
@@ -353,6 +354,7 @@ extern int mce_threshold_remove_device(unsigned int cpu);
 static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
 static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
 static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
+static inline bool filter_mce_amd(struct mce *m) { return false; };
 
 #endif
 
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index e64de5149e50..819d5dd41925 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -563,22 +563,52 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 	return offset;
 }
 
+bool filter_mce_amd(struct mce *m)
+{
+	enum smca_bank_types bank_type = smca_get_bank_type(m->bank);
+	struct cpuinfo_x86 *c = &boot_cpu_data;
+	u8 xec = (m->status >> 16) & 0x3F;
+
+	/*
+	 * Spurious errors of this type may be reported.
+	 * See Family 17h Models 10h-2Fh Erratum #1114.
+	 */
+	if (c->x86 == 0x17 &&
+	    c->x86_model >= 0x10 && c->x86_model <= 0x2F &&
+	    bank_type == SMCA_IF && xec == 10)
+		return true;
+
+	return false;
+}
+
 /*
- * Turn off MC4_MISC thresholding banks on all family 0x15 models since
- * they're not supported there.
+ * Turn off thresholding banks for the following conditions:
+ * - MC4_MISC thresholding is not support on Family 0x15.
+ * - Prevent possible spurious interrupts from the IF bank on Family 0x17
+ *   Models 0x10-0x2F due to Erratum #1114.
  */
-void disable_err_thresholding(struct cpuinfo_x86 *c)
+void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)
 {
-	int i;
+	int i, num_msrs;
 	u64 hwcr;
 	bool need_toggle;
-	u32 msrs[] = {
-		0x00000413, /* MC4_MISC0 */
-		0xc0000408, /* MC4_MISC1 */
-	};
+	u32 msrs[NR_BLOCKS];
+
+	if (c->x86 == 0x15 && bank == 4) {
+		msrs[0] = 0x00000413; /* MC4_MISC0 */
+		msrs[1] = 0xc0000408; /* MC4_MISC1 */
+		num_msrs = 2;
+	} else if (c->x86 == 0x17 &&
+		   (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) {
+
+		if (smca_get_bank_type(bank) != SMCA_IF)
+			return;
 
-	if (c->x86 != 0x15)
+		msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank);
+		num_msrs = 1;
+	} else {
 		return;
+	}
 
 	rdmsrl(MSR_K7_HWCR, hwcr);
 
@@ -589,7 +619,7 @@ void disable_err_thresholding(struct cpuinfo_x86 *c)
 		wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
 
 	/* Clear CntP bit safely */
-	for (i = 0; i < ARRAY_SIZE(msrs); i++)
+	for (i = 0; i < num_msrs; i++)
 		msr_clear_bit(msrs[i], 62);
 
 	/* restore old settings */
@@ -604,12 +634,12 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 	unsigned int bank, block, cpu = smp_processor_id();
 	int offset = -1;
 
-	disable_err_thresholding(c);
-
 	for (bank = 0; bank < mca_cfg.banks; ++bank) {
 		if (mce_flags.smca)
 			smca_configure(bank, cpu);
 
+		disable_err_thresholding(c, bank);
+
 		for (block = 0; block < NR_BLOCKS; ++block) {
 			address = get_block_address(address, low, high, bank, block);
 			if (!address)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 12d61b8f8154..ebc619a20c87 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1773,6 +1773,9 @@ static void __mcheck_cpu_init_timer(void)
 
 bool filter_mce(struct mce *m)
 {
+	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+		return filter_mce_amd(m);
+
 	return false;
 }
 
-- 
2.17.1

[PATCH v3 3/3] x86/MCE: Group AMD function prototypes in <asm/mce.h>

[Ghannam, Yazen]

From: Yazen Ghannam <yazen.ghannam@amd.com>

There are two groups of "ifdef CONFIG_X86_MCE_AMD" function prototypes
in <asm/mce.h>.

Merge these two groups.

No functional change.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
v2->v3
* This patch is new and unrelated to the other two. I just happened to
  notice this issue when making other changes.

 arch/x86/include/asm/mce.h | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 50f76a7956cc..acb76ca7a23c 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -210,16 +210,6 @@ static inline void cmci_rediscover(void) {}
 static inline void cmci_recheck(void) {}
 #endif
 
-#ifdef CONFIG_X86_MCE_AMD
-void mce_amd_feature_init(struct cpuinfo_x86 *c);
-int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
-#else
-static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
-static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
-#endif
-
-static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
-
 int mce_available(struct cpuinfo_x86 *c);
 bool mce_is_memory_error(struct mce *m);
 bool mce_is_correctable(struct mce *m);
@@ -349,13 +339,20 @@ extern bool filter_mce_amd(struct mce *m);
 extern int mce_threshold_create_device(unsigned int cpu);
 extern int mce_threshold_remove_device(unsigned int cpu);
 
+void mce_amd_feature_init(struct cpuinfo_x86 *c);
+int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
+
 #else
 
 static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
 static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
 static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
 static inline bool filter_mce_amd(struct mce *m) { return false; };
+static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
+static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
 
 #endif
 
+static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
+
 #endif /* _ASM_X86_MCE_H */
-- 
2.17.1

Re: [PATCH v3 2/3] x86/MCE/AMD: Don't report L1 BTB MCA errors on some Family 17h models

[Ghannam, Yazen]

On 3/22/2019 3:28 PM, Ghannam, Yazen wrote:
> From: Yazen Ghannam <yazen.ghannam@amd.com>
> 
> AMD Family 17h Models 10h-2Fh may report a high number of L1 BTB MCA
> errors under certain conditions. The errors are benign and can safely be
> ignored. However, the high error rate may cause the MCA threshold
> counter to overflow causing a high rate of thresholding interrupts. In
> addition, users may see the errors reported through the AMD MCE decoder
> module, even with the interrupt disabled, due to MCA polling.
> 
> This error is reported through the Instruction Fetch bank.
> 
> Clear the "Counter Present" bit in the Instruction Fetch bank's
> MCA_MISC0 register. This will prevent enabling MCA thresholding on this
> bank which will prevent the high interrupt rate due to this error.
> 
> Define an AMD-specific function to filter these errors from the MCE
> event pool.
> 
> Cc: <stable@vger.kernel.org> # 4.14.x: c95b323dcd35: x86/MCE/AMD: Turn off MC4_MISC thresholding on all family 0x15 models
> Cc: <stable@vger.kernel.org> # 4.14.x: 30aa3d26edb0: x86/MCE/AMD: Carve out the MC4_MISC thresholding quirk
> Cc: <stable@vger.kernel.org> # 4.14.x
> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
> ---
> Link:
> https://lkml.kernel.org/r/20190321202505.5553-2-Yazen.Ghannam@amd.com
> 
> v2->v3:
> * Define a simple AMD-specific filter function rather than a
>   model-specific one.
> 
> v1->v2:
> * Filter out the error earlier in MCE code rather than later in EDAC.
> 
>  arch/x86/include/asm/mce.h     |  2 ++
>  arch/x86/kernel/cpu/mce/amd.c  | 54 ++++++++++++++++++++++++++--------
>  arch/x86/kernel/cpu/mce/core.c |  3 ++
>  3 files changed, 47 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
> index ec5bf1cad217..50f76a7956cc 100644
> --- a/arch/x86/include/asm/mce.h
> +++ b/arch/x86/include/asm/mce.h
> @@ -344,6 +344,7 @@ extern struct smca_bank smca_banks[MAX_NR_BANKS];
>  
>  extern const char *smca_get_long_name(enum smca_bank_types t);
>  extern bool amd_mce_is_memory_error(struct mce *m);
> +extern bool filter_mce_amd(struct mce *m);
>  
>  extern int mce_threshold_create_device(unsigned int cpu);
>  extern int mce_threshold_remove_device(unsigned int cpu);
> @@ -353,6 +354,7 @@ extern int mce_threshold_remove_device(unsigned int cpu);
>  static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
>  static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
>  static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
> +static inline bool filter_mce_amd(struct mce *m) { return false; };
>  

Sorry, I forgot to mention this. I went with "filter_mce_amd" because amd_filter_mce() is already defined in edac/mce_amd.c and there was a conflict when building. Is there another way to avoid these naming conflicts?

Thanks,
Yazen

>  #endif
>  
> diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
> index e64de5149e50..819d5dd41925 100644
> --- a/arch/x86/kernel/cpu/mce/amd.c
> +++ b/arch/x86/kernel/cpu/mce/amd.c
> @@ -563,22 +563,52 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
>  	return offset;
>  }
>  
> +bool filter_mce_amd(struct mce *m)
> +{
> +	enum smca_bank_types bank_type = smca_get_bank_type(m->bank);
> +	struct cpuinfo_x86 *c = &boot_cpu_data;
> +	u8 xec = (m->status >> 16) & 0x3F;
> +
> +	/*
> +	 * Spurious errors of this type may be reported.
> +	 * See Family 17h Models 10h-2Fh Erratum #1114.
> +	 */
> +	if (c->x86 == 0x17 &&
> +	    c->x86_model >= 0x10 && c->x86_model <= 0x2F &&
> +	    bank_type == SMCA_IF && xec == 10)
> +		return true;
> +
> +	return false;
> +}
> +
>  /*
> - * Turn off MC4_MISC thresholding banks on all family 0x15 models since
> - * they're not supported there.
> + * Turn off thresholding banks for the following conditions:
> + * - MC4_MISC thresholding is not support on Family 0x15.
> + * - Prevent possible spurious interrupts from the IF bank on Family 0x17
> + *   Models 0x10-0x2F due to Erratum #1114.
>   */
> -void disable_err_thresholding(struct cpuinfo_x86 *c)
> +void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)
>  {
> -	int i;
> +	int i, num_msrs;
>  	u64 hwcr;
>  	bool need_toggle;
> -	u32 msrs[] = {
> -		0x00000413, /* MC4_MISC0 */
> -		0xc0000408, /* MC4_MISC1 */
> -	};
> +	u32 msrs[NR_BLOCKS];
> +
> +	if (c->x86 == 0x15 && bank == 4) {
> +		msrs[0] = 0x00000413; /* MC4_MISC0 */
> +		msrs[1] = 0xc0000408; /* MC4_MISC1 */
> +		num_msrs = 2;
> +	} else if (c->x86 == 0x17 &&
> +		   (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) {
> +
> +		if (smca_get_bank_type(bank) != SMCA_IF)
> +			return;
>  
> -	if (c->x86 != 0x15)
> +		msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank);
> +		num_msrs = 1;
> +	} else {
>  		return;
> +	}
>  
>  	rdmsrl(MSR_K7_HWCR, hwcr);
>  
> @@ -589,7 +619,7 @@ void disable_err_thresholding(struct cpuinfo_x86 *c)
>  		wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
>  
>  	/* Clear CntP bit safely */
> -	for (i = 0; i < ARRAY_SIZE(msrs); i++)
> +	for (i = 0; i < num_msrs; i++)
>  		msr_clear_bit(msrs[i], 62);
>  
>  	/* restore old settings */
> @@ -604,12 +634,12 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
>  	unsigned int bank, block, cpu = smp_processor_id();
>  	int offset = -1;
>  
> -	disable_err_thresholding(c);
> -
>  	for (bank = 0; bank < mca_cfg.banks; ++bank) {
>  		if (mce_flags.smca)
>  			smca_configure(bank, cpu);
>  
> +		disable_err_thresholding(c, bank);
> +
>  		for (block = 0; block < NR_BLOCKS; ++block) {
>  			address = get_block_address(address, low, high, bank, block);
>  			if (!address)
> diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
> index 12d61b8f8154..ebc619a20c87 100644
> --- a/arch/x86/kernel/cpu/mce/core.c
> +++ b/arch/x86/kernel/cpu/mce/core.c
> @@ -1773,6 +1773,9 @@ static void __mcheck_cpu_init_timer(void)
>  
>  bool filter_mce(struct mce *m)
>  {
> +	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
> +		return filter_mce_amd(m);
> +
>  	return false;
>  }
>  
> 

Re: [PATCH v3 2/3] x86/MCE/AMD: Don't report L1 BTB MCA errors on some Family 17h models

[Borislav Petkov]

On Fri, Mar 22, 2019 at 08:37:08PM +0000, Ghannam, Yazen wrote:
> Sorry, I forgot to mention this. I went with "filter_mce_amd" because
> amd_filter_mce() is already defined in edac/mce_amd.c and there was
> a conflict when building. Is there another way to avoid these naming
> conflicts?

Yuck, we're clearly filtering too much. :)

So let's rename that amd_filter_mce() to something else since it is
static and only used in that file. Maybe something like

        if (ignore_mce(m))
                return NOTIFY_STOP;

so that we can keep the "filter" notion all reserved to the core MCA
code and there's no confusion.

And then amd_filter_mce() is free to be used in the core code.

Thx.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

RE: [PATCH v3 2/3] x86/MCE/AMD: Don't report L1 BTB MCA errors on some Family 17h models

[Ghannam, Yazen]

> -----Original Message-----
> From: linux-edac-owner@vger.kernel.org <linux-edac-owner@vger.kernel.org> On Behalf Of Borislav Petkov
> Sent: Friday, March 22, 2019 3:55 PM
> To: Ghannam, Yazen <Yazen.Ghannam@amd.com>
> Cc: linux-edac@vger.kernel.org; linux-kernel@vger.kernel.org; tony.luck@intel.com; x86@kernel.org; rafal@milecki.pl;
> clemej@gmail.com
> Subject: Re: [PATCH v3 2/3] x86/MCE/AMD: Don't report L1 BTB MCA errors on some Family 17h models
> 
> On Fri, Mar 22, 2019 at 08:37:08PM +0000, Ghannam, Yazen wrote:
> > Sorry, I forgot to mention this. I went with "filter_mce_amd" because
> > amd_filter_mce() is already defined in edac/mce_amd.c and there was
> > a conflict when building. Is there another way to avoid these naming
> > conflicts?
> 
> Yuck, we're clearly filtering too much. :)
> 
> So let's rename that amd_filter_mce() to something else since it is
> static and only used in that file. Maybe something like
> 
>         if (ignore_mce(m))
>                 return NOTIFY_STOP;
> 
> so that we can keep the "filter" notion all reserved to the core MCA
> code and there's no confusion.
> 
> And then amd_filter_mce() is free to be used in the core code.
> 

Okay, will do.

Should this be a pre-patch, or just include it here?

Thanks,
Yazen

Re: [PATCH v3 2/3] x86/MCE/AMD: Don't report L1 BTB MCA errors on some Family 17h models

[Borislav Petkov]

On Fri, Mar 22, 2019 at 09:35:41PM +0000, Ghannam, Yazen wrote:
> Should this be a pre-patch, or just include it here?

Should be small enough so you can include it with this one.

Thx.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

[tip:ras/core] x86/MCE: Group AMD function prototypes in <asm/mce.h>

[tip-bot for Yazen Ghannam]

Commit-ID:  9308fd4074551f222f30322d1ee8c5aff18e9747
Gitweb:     https://git.kernel.org/tip/9308fd4074551f222f30322d1ee8c5aff18e9747
Author:     Yazen Ghannam <yazen.ghannam@amd.com>
AuthorDate: Fri, 22 Mar 2019 20:29:00 +0000
Committer:  Borislav Petkov <bp@suse.de>
CommitDate: Sun, 24 Mar 2019 10:54:13 +0100

x86/MCE: Group AMD function prototypes in <asm/mce.h>

There are two groups of "ifdef CONFIG_X86_MCE_AMD" function prototypes
in <asm/mce.h>. Merge these two groups.

No functional change.

 [ bp: align vertically. ]

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "clemej@gmail.com" <clemej@gmail.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Pu Wen <puwen@hygon.cn>
Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Cc: "rafal@milecki.pl" <rafal@milecki.pl>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/20190322202848.20749-3-Yazen.Ghannam@amd.com
---
 arch/x86/include/asm/mce.h | 25 +++++++++++--------------
 1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 22d05e3835f0..dc2d4b206ab7 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -210,16 +210,6 @@ static inline void cmci_rediscover(void) {}
 static inline void cmci_recheck(void) {}
 #endif
 
-#ifdef CONFIG_X86_MCE_AMD
-void mce_amd_feature_init(struct cpuinfo_x86 *c);
-int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
-#else
-static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
-static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
-#endif
-
-static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
-
 int mce_available(struct cpuinfo_x86 *c);
 bool mce_is_memory_error(struct mce *m);
 bool mce_is_correctable(struct mce *m);
@@ -345,12 +335,19 @@ extern bool amd_mce_is_memory_error(struct mce *m);
 extern int mce_threshold_create_device(unsigned int cpu);
 extern int mce_threshold_remove_device(unsigned int cpu);
 
-#else
+void mce_amd_feature_init(struct cpuinfo_x86 *c);
+int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
 
-static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
-static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
-static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
+#else
 
+static inline int mce_threshold_create_device(unsigned int cpu)		{ return 0; };
+static inline int mce_threshold_remove_device(unsigned int cpu)		{ return 0; };
+static inline bool amd_mce_is_memory_error(struct mce *m)		{ return false; };
+static inline void mce_amd_feature_init(struct cpuinfo_x86 *c)		{ }
+static inline int
+umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)	{ return -EINVAL; };
 #endif
 
+static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c)	{ return mce_amd_feature_init(c); }
+
 #endif /* _ASM_X86_MCE_H */