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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id t66sm9878666oig.39.2019.03.28.08.12.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Mar 2019 08:12:56 -0700 (PDT) Date: Thu, 28 Mar 2019 10:12:55 -0500 From: Rob Herring To: Georgi Djakov Cc: vireshk@kernel.org, sboyd@kernel.org, nm@ti.com, mark.rutland@arm.com, rjw@rjwysocki.net, jcrouse@codeaurora.org, vincent.guittot@linaro.org, bjorn.andersson@linaro.org, amit.kucheria@linaro.org, seansw@qti.qualcomm.com, daidavid1@codeaurora.org, evgreen@chromium.org, sibis@codeaurora.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH 1/4] dt-bindings: opp: Introduce opp-bw-MBs bindings Message-ID: <20190328151255.GA5262@bogus> References: <20190313090010.20534-1-georgi.djakov@linaro.org> <20190313090010.20534-2-georgi.djakov@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190313090010.20534-2-georgi.djakov@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Mar 13, 2019 at 11:00:07AM +0200, Georgi Djakov wrote: > In addition to frequency and voltage, some devices may have bandwidth > requirements for their interconnect throughput - for example a CPU > or GPU may also need to increase or decrease their bandwidth to DDR > memory based on the current operating performance point. > > Extend the OPP tables with additional property to describe the bandwidth > needs of a device. The average and peak bandwidth values depend on the > hardware and its properties. How would this work if you have 1 OPP (for the bus/interconnect/ddr) and 2 devices with variable bandwidth needs? Or 'device' here means the interconnect? > > Signed-off-by: Georgi Djakov > --- > Documentation/devicetree/bindings/opp/opp.txt | 45 +++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt > index 76b6c79604a5..fa598264615f 100644 > --- a/Documentation/devicetree/bindings/opp/opp.txt > +++ b/Documentation/devicetree/bindings/opp/opp.txt > @@ -129,6 +129,9 @@ Optional properties: > - opp-microamp-: Named opp-microamp property. Similar to > opp-microvolt- property, but for microamp instead. > > +- opp-bw-MBs: The interconnect bandwidth is specified with an array containing > + the two integer values for average and peak bandwidth in megabytes per second. -MBps would be better IMO. Either way, units should be documented in property-units.txt. > + > - opp-level: A value representing the performance level of the device, > expressed as a 32-bit integer. > > @@ -546,3 +549,45 @@ Example 6: opp-microvolt-, opp-microamp-: > }; > }; > }; > + > +Example 7: opp-bw-MBs: > +(example: average and peak bandwidth values are defined for each OPP and the > +interconnect between CPU and DDR memory is scaled together with CPU frequency) > + > +/ { > + cpus { > + CPU0: cpu@0 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + ... > + operating-points-v2 = <&cpu_opp_table>; > + /* path between the CPU and DDR memory */ > + interconnects = <&rpm_bimc MASTER_AMPSS_M0 > + &rpm_bimc SLAVE_EBI_CH0>; > + }; > + }; > + > + cpu_opp_table: cpu_opp_table { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + /* 457 MB/s average and 1525 MB/s peak bandwidth */ > + opp-bw-MBs = <457 1525>; > + }; > + opp-400000000 { > + opp-hz = /bits/ 64 <400000000>; > + /* 915 MB/s average and 3051 MB/s peak bandwidth */ > + opp-bw-MBs = <915 3051>; > + }; > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + /* 1830 MB/s average and 6103 MB/s peak bandwidth */ > + opp-bw-MBs = <1830 6103>; > + }; > + opp-998400000 { > + opp-hz = /bits/ 64 <998400000>; > + /* 2282 MB/s average and 7614 MB/s peak bandwidth */ > + opp-bw-MBs = <2284 7614>; > + }; > + };