From: Will Deacon <will.deacon@arm.com>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Cc: lorenzo.pieralisi@arm.com, robin.murphy@arm.com,
andrew.murray@arm.com, jean-philippe.brucker@arm.com,
mark.rutland@arm.com, guohanjun@huawei.com,
john.garry@huawei.com, pabba@codeaurora.org,
vkilari@codeaurora.org, rruigrok@codeaurora.org,
linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com,
neil.m.leeder@gmail.com
Subject: Re: [PATCH v7 2/4] perf/smmuv3: Add arm64 smmuv3 pmu driver
Date: Thu, 4 Apr 2019 16:30:20 +0100 [thread overview]
Message-ID: <20190404153020.GD27558@fuggles.cambridge.arm.com> (raw)
In-Reply-To: <20190326151753.19384-3-shameerali.kolothum.thodi@huawei.com>
On Tue, Mar 26, 2019 at 03:17:51PM +0000, Shameer Kolothum wrote:
> From: Neil Leeder <nleeder@codeaurora.org>
>
> Adds a new driver to support the SMMUv3 PMU and add it into the
> perf events framework.
>
> Each SMMU node may have multiple PMUs associated with it, each of
> which may support different events.
>
> SMMUv3 PMCG devices are named as smmuv3_pmcg_<phys_addr_page> where
> <phys_addr_page> is the physical page address of the SMMU PMCG
> wrapped to 4K boundary. For example, the PMCG at 0xff88840000 is
> named smmuv3_pmcg_ff88840
>
> Filtering by stream id is done by specifying filtering parameters
> with the event. options are:
> filter_enable - 0 = no filtering, 1 = filtering enabled
> filter_span - 0 = exact match, 1 = pattern match
> filter_stream_id - pattern to filter against
>
> Example: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1,
> filter_span=1,filter_stream_id=0x42/ -a netperf
>
> Applies filter pattern 0x42 to transaction events, which means events
> matching stream ids 0x42 & 0x43 are counted as only upper StreamID
> bits are required to match the given filter. Further filtering
> information is available in the SMMU documentation.
>
> SMMU events are not attributable to a CPU, so task mode and sampling
> are not supported.
>
> Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> ---
> drivers/perf/Kconfig | 9 +
> drivers/perf/Makefile | 1 +
> drivers/perf/arm_smmuv3_pmu.c | 776 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 786 insertions(+)
> create mode 100644 drivers/perf/arm_smmuv3_pmu.c
[...]
> +static int smmu_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
> +{
> + struct smmu_pmu *smmu_pmu;
> + unsigned int target;
> +
> + smmu_pmu = hlist_entry_safe(node, struct smmu_pmu, node);
> + if (cpu != smmu_pmu->on_cpu)
> + return 0;
> +
> + target = cpumask_any_but(cpu_online_mask, cpu);
> + if (target >= nr_cpu_ids)
> + return 0;
> +
> + perf_pmu_migrate_context(&smmu_pmu->pmu, cpu, target);
> + smmu_pmu->on_cpu = target;
> + WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(target)));
I'm going to make this (and the other invocation) use
irq_set_affinity_hint() instead, so that we can build this driver as a
module with the appropriate Kconfig tweak.
Will
next prev parent reply other threads:[~2019-04-04 15:30 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-26 15:17 [PATCH v7 0/4] arm64 SMMUv3 PMU driver with IORT support Shameer Kolothum
2019-03-26 15:17 ` [PATCH v7 1/4] ACPI/IORT: Add support for PMCG Shameer Kolothum
2019-03-26 15:17 ` [PATCH v7 2/4] perf/smmuv3: Add arm64 smmuv3 pmu driver Shameer Kolothum
2019-03-26 16:57 ` Robin Murphy
2019-03-26 17:02 ` Shameerali Kolothum Thodi
2019-04-04 15:30 ` Will Deacon [this message]
2019-03-26 15:17 ` [PATCH v7 3/4] perf/smmuv3: Add MSI irq support Shameer Kolothum
2019-03-26 15:17 ` [PATCH v7 4/4] perf/smmuv3: Enable HiSilicon Erratum 162001800 quirk Shameer Kolothum
2019-04-04 12:32 ` Will Deacon
2019-04-04 14:49 ` Lorenzo Pieralisi
2019-04-04 15:47 ` Will Deacon
2019-04-04 16:31 ` Shameerali Kolothum Thodi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190404153020.GD27558@fuggles.cambridge.arm.com \
--to=will.deacon@arm.com \
--cc=andrew.murray@arm.com \
--cc=guohanjun@huawei.com \
--cc=jean-philippe.brucker@arm.com \
--cc=john.garry@huawei.com \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linuxarm@huawei.com \
--cc=lorenzo.pieralisi@arm.com \
--cc=mark.rutland@arm.com \
--cc=neil.m.leeder@gmail.com \
--cc=pabba@codeaurora.org \
--cc=robin.murphy@arm.com \
--cc=rruigrok@codeaurora.org \
--cc=shameerali.kolothum.thodi@huawei.com \
--cc=vkilari@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).