From: megous@megous.com
To: linux-sunxi@googlegroups.com,
Maxime Ripard <maxime.ripard@bootlin.com>,
Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>
Cc: Ondrej Jirman <megous@megous.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Mark Rutland <mark.rutland@arm.com>,
Giuseppe Cavallaro <peppe.cavallaro@st.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
Jose Abreu <joabreu@synopsys.com>,
"David S. Miller" <davem@davemloft.net>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Arend van Spriel <arend.vanspriel@broadcom.com>,
Franky Lin <franky.lin@broadcom.com>,
Hante Meuleman <hante.meuleman@broadcom.com>,
Chi-Hsien Lin <chi-hsien.lin@cypress.com>,
Wright Feng <wright.feng@cypress.com>,
Kalle Valo <kvalo@codeaurora.org>,
Naveen Gupta <naveen.gupta@cypress.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-wireless@vger.kernel.org,
brcm80211-dev-list.pdl@broadcom.com,
brcm80211-dev-list@cypress.com, linux-gpio@vger.kernel.org
Subject: [PATCH v2 06/13] pinctrl: sunxi: Support I/O bias voltage setting on H6
Date: Tue, 9 Apr 2019 02:24:45 +0200 [thread overview]
Message-ID: <20190409002452.14551-7-megous@megous.com> (raw)
In-Reply-To: <20190409002452.14551-1-megous@megous.com>
From: Ondrej Jirman <megous@megous.com>
H6 SoC has a "pio group withstand voltage mode" register (datasheet
description), that needs to be used to select either 1.8V or 3.3V I/O mode,
based on what voltage is powering the respective pin banks and is thus used
for I/O signals.
Add support for configuring this register according to the voltage of the
pin bank regulator (if enabled).
This is similar to the support for I/O bias voltage setting patch for A80
and the same concerns apply. See:
commit 402bfb3c1352 ("Support I/O bias voltage setting on A80")
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 +
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 10 ++++++++++
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 4 ++++
3 files changed, 15 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
index ef4268cc6227..30b1befa8ed8 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
@@ -591,6 +591,7 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
.irq_banks = 4,
.irq_bank_map = h6_irq_bank_map,
.irq_read_needs_mux = true,
+ .io_bias_cfg_variant = IO_BIAS_CFG_V2,
};
static int h6_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index b8dd58ef33b7..0ab50a15a716 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -607,6 +607,8 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
unsigned pin,
struct regulator *supply)
{
+ unsigned short bank = pin / PINS_PER_BANK;
+ unsigned long flags;
u32 val, reg;
int uV;
@@ -642,6 +644,14 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
reg &= ~IO_BIAS_MASK;
writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
+ } else if (pctl->desc->io_bias_cfg_variant == IO_BIAS_CFG_V2) {
+ val = uV <= 1800000 ? 1 : 0;
+
+ raw_spin_lock_irqsave(&pctl->lock, flags);
+ reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
+ reg &= ~(1 << bank);
+ writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
}
return 0;
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index 642f667e99d2..4044a3cb1819 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -95,8 +95,12 @@
#define PINCTRL_SUN7I_A20 BIT(7)
#define PINCTRL_SUN8I_R40 BIT(8)
+#define PIO_POW_MOD_SEL_REG 0x340
+
/* Bias voltage configuration done via Pn_GRP_CONFIG registers. */
#define IO_BIAS_CFG_V1 1
+/* Bias voltage set in the PIO_POW_MOD_SEL_REG register. */
+#define IO_BIAS_CFG_V2 2
struct sunxi_desc_function {
unsigned long variant;
--
2.21.0
next prev parent reply other threads:[~2019-04-09 0:26 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-09 0:24 [PATCH v2 00/13] Add support for Orange Pi 3 megous
2019-04-09 0:24 ` [PATCH v2 01/13] dt-bindings: sunxi: Add compatible for OrangePi 3 board megous
2019-04-09 8:10 ` Maxime Ripard
2019-04-09 0:24 ` [PATCH v2 02/13] arm64: dts: allwinner: h6: Add Orange Pi 3 DTS megous
2019-04-09 8:12 ` Maxime Ripard
2019-04-09 9:33 ` Ondřej Jirman
2019-04-09 11:59 ` Maxime Ripard
2019-04-09 8:38 ` [linux-sunxi] " Jagan Teki
2019-04-09 11:31 ` Ondřej Jirman
2019-04-09 11:47 ` Maxime Ripard
2019-04-09 13:27 ` Jagan Teki
2019-04-09 0:24 ` [PATCH v2 03/13] net: stmmac: sun8i: add support for Allwinner H6 EMAC megous
2019-04-09 0:24 ` [PATCH v2 04/13] net: stmmac: sun8i: force select external PHY when no internal one megous
2019-04-09 0:24 ` [PATCH v2 05/13] pinctrl: sunxi: Prepare for alternative bias voltage setting methods megous
2019-04-09 8:43 ` Maxime Ripard
2019-04-09 0:24 ` megous [this message]
2019-04-09 0:24 ` [PATCH v2 07/13] arm64: dts: allwinner: orange-pi-3: Enable ethernet megous
2019-04-09 0:24 ` [PATCH v2 08/13] drm: sun4i: Add support for enabling DDC I2C bus to dw_hdmi glue megous
2019-04-09 0:24 ` [PATCH v2 09/13] dt-bindings: display: sun4i-drm: Add DDC power supply megous
2019-04-09 0:24 ` [PATCH v2 10/13] arm64: dts: allwinner: orange-pi-3: Enable HDMI output megous
2019-04-09 0:24 ` [PATCH v2 11/13] brcmfmac: Loading the correct firmware for brcm43456 megous
2019-04-09 0:24 ` [PATCH v2 12/13] [DO NOT MERGE] arm64: dts: allwinner: h6: Add MMC1 pins megous
2019-04-09 0:24 ` [PATCH v2 13/13] [DO NOT MERGE] arm64: dts: allwinner: orange-pi-3: Enable WiFi megous
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