From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AACEC10F0E for ; Fri, 12 Apr 2019 15:55:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CF8B220850 for ; Fri, 12 Apr 2019 15:55:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726963AbfDLPzw (ORCPT ); Fri, 12 Apr 2019 11:55:52 -0400 Received: from foss.arm.com ([217.140.101.70]:35360 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726702AbfDLPzw (ORCPT ); Fri, 12 Apr 2019 11:55:52 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2A3AE15AB; Fri, 12 Apr 2019 08:55:51 -0700 (PDT) Received: from e110455-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C865D3F557; Fri, 12 Apr 2019 08:55:50 -0700 (PDT) Received: by e110455-lin.cambridge.arm.com (Postfix, from userid 1000) id 23EE868012C; Fri, 12 Apr 2019 16:55:49 +0100 (BST) Date: Fri, 12 Apr 2019 16:55:49 +0100 From: Liviu Dudau To: Ben Davis Cc: "dri-devel@lists.freedesktop.org" , nd , Brian Starkey , "airlied@linux.ie" , "daniel@ffwll.ch" , "maarten.lankhorst@linux.intel.com" , "maxime.ripard@bootlin.com" , "sean@poorly.run" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v2 2/2] drm/malidp: Enable writeback scaling Message-ID: <20190412155548.GN15144@e110455-lin.cambridge.arm.com> References: <1555078094-6587-1-git-send-email-ben.davis@arm.com> <1555078094-6587-3-git-send-email-ben.davis@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1555078094-6587-3-git-send-email-ben.davis@arm.com> User-Agent: Mutt/1.11.4 (2019-03-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Ben, On Fri, Apr 12, 2019 at 03:08:32PM +0100, Ben Davis wrote: > The phase setting part of malidp_crtc_atomic_check_scaling is refactored > to allow use in writeback scaling. > > Also the enable_memwrite function prototype is simplified by directly > passing mw_state. > > Signed-off-by: Ben Davis > --- > drivers/gpu/drm/arm/malidp_crtc.c | 49 ++++++++++++---------- > drivers/gpu/drm/arm/malidp_crtc.h | 12 ++++++ > drivers/gpu/drm/arm/malidp_drv.c | 10 +++-- > drivers/gpu/drm/arm/malidp_hw.c | 45 ++++++++++++++------ > drivers/gpu/drm/arm/malidp_hw.h | 19 +++++++-- > drivers/gpu/drm/arm/malidp_mw.c | 86 ++++++++++++++++++++++++++++++--------- > drivers/gpu/drm/arm/malidp_regs.h | 1 + > 7 files changed, 161 insertions(+), 61 deletions(-) > create mode 100644 drivers/gpu/drm/arm/malidp_crtc.h > > diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c > index 3f65996..aa66457 100644 > --- a/drivers/gpu/drm/arm/malidp_crtc.c > +++ b/drivers/gpu/drm/arm/malidp_crtc.c > @@ -265,6 +265,31 @@ static int malidp_crtc_atomic_check_ctm(struct drm_crtc *crtc, > return 0; > } > > +void malidp_set_se_config_phase(struct malidp_se_config *s) > +{ > +#define SE_N_PHASE 4 > +#define SE_SHIFT_N_PHASE 12 > + u32 phase; > + > + /* Calculate initial_phase and delta_phase for horizontal. */ > + phase = s->input_w; > + s->h_init_phase = ((phase << SE_N_PHASE) / s->output_w + 1) / 2; > + > + phase = s->input_w; > + phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE); > + s->h_delta_phase = phase / s->output_w; > + > + /* Same for vertical. */ > + phase = s->input_h; > + s->v_init_phase = ((phase << SE_N_PHASE) / s->output_h + 1) / 2; > + > + phase = s->input_h; > + phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE); > + s->v_delta_phase = phase / s->output_h; > +#undef SE_N_PHASE > +#undef SE_SHIFT_N_PHASE > +} > + > static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc, > struct drm_crtc_state *state) > { > @@ -291,7 +316,6 @@ static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc, > > drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { > struct malidp_plane *mp = to_malidp_plane(plane); > - u32 phase; > > if (!(mp->layer->id & scaling)) > continue; > @@ -319,27 +343,8 @@ static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc, > s->output_w = pstate->crtc_w; > s->output_h = pstate->crtc_h; > > -#define SE_N_PHASE 4 > -#define SE_SHIFT_N_PHASE 12 > - /* Calculate initial_phase and delta_phase for horizontal. */ > - phase = s->input_w; > - s->h_init_phase = > - ((phase << SE_N_PHASE) / s->output_w + 1) / 2; > - > - phase = s->input_w; > - phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE); > - s->h_delta_phase = phase / s->output_w; > - > - /* Same for vertical. */ > - phase = s->input_h; > - s->v_init_phase = > - ((phase << SE_N_PHASE) / s->output_h + 1) / 2; > - > - phase = s->input_h; > - phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE); > - s->v_delta_phase = phase / s->output_h; > -#undef SE_N_PHASE > -#undef SE_SHIFT_N_PHASE > + > + malidp_set_se_config_phase(s); > s->plane_src_id = mp->layer->id; > } > > diff --git a/drivers/gpu/drm/arm/malidp_crtc.h b/drivers/gpu/drm/arm/malidp_crtc.h > new file mode 100644 > index 0000000..0f056f8 > --- /dev/null > +++ b/drivers/gpu/drm/arm/malidp_crtc.h > @@ -0,0 +1,12 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * (C) COPYRIGHT 2019 ARM Limited. All rights reserved. > + * > + */ > + > +#include "malidp_hw.h" > + > +#ifndef __MALIDP_CRTC_H__ > +#define __MALIDP_CRTC_H__ > +void malidp_set_se_config_phase(struct malidp_se_config *s); > +#endif > diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c > index d37ff9d..e2465e9 100644 > --- a/drivers/gpu/drm/arm/malidp_drv.c > +++ b/drivers/gpu/drm/arm/malidp_drv.c > @@ -138,7 +138,7 @@ static void malidp_atomic_commit_se_config(struct drm_crtc *crtc, > u32 val; > > /* Set SE_CONTROL */ > - if (!s->scale_enable) { > + if (!s->scale_enable && !s->wb_scale_enable) { > val = malidp_hw_read(hwdev, se_control); > val &= ~MALIDP_SE_SCALING_EN; > malidp_hw_write(hwdev, val, se_control); > @@ -147,12 +147,16 @@ static void malidp_atomic_commit_se_config(struct drm_crtc *crtc, > > hwdev->hw->se_set_scaling_coeffs(hwdev, s, old_s); > val = malidp_hw_read(hwdev, se_control); > - val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN; > + val |= MALIDP_SE_SCALING_EN; > > val &= ~MALIDP_SE_ENH(MALIDP_SE_ENH_MASK); > val |= s->enhancer_enable ? MALIDP_SE_ENH(3) : 0; > > - val |= MALIDP_SE_RGBO_IF_EN; > + if (s->scale_enable) > + val |= (MALIDP_SE_RGBO_IF_EN | MALIDP_SE_ALPHA_EN); > + else > + val &= ~((MALIDP_SE_RGBO_IF_EN | MALIDP_SE_ALPHA_EN)); > + > malidp_hw_write(hwdev, val, se_control); > > /* Set IN_SIZE & OUT_SIZE. */ > diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c > index 1a36718..6f59c0e 100644 > --- a/drivers/gpu/drm/arm/malidp_hw.c > +++ b/drivers/gpu/drm/arm/malidp_hw.c > @@ -497,13 +497,18 @@ static long malidp500_se_calc_mclk(struct malidp_hw_device *hwdev, > return ret; > } > > -static int malidp500_enable_memwrite(struct malidp_hw_device *hwdev, > - dma_addr_t *addrs, s32 *pitches, > - int num_planes, u16 w, u16 h, u32 fmt_id, > - const s16 *rgb2yuv_coeffs) > +static int malidp500_enable_memwrite(struct malidp_hw_device *hwdev, u16 w, u16 h, > + struct malidp_mw_connector_state *mw_state) > { > + > + int num_planes = mw_state->n_planes; > + dma_addr_t *addrs = mw_state->addrs; > + s32 *pitches = mw_state->pitches; > + u32 fmt_id = mw_state->format; > u32 base = MALIDP500_SE_MEMWRITE_BASE; > u32 de_base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); > + const s16 *rgb2yuv_coeffs = !mw_state->rgb2yuv_initialized ? > + mw_state->rgb2yuv_coeffs : NULL; > > /* enable the scaling engine block */ > malidp_hw_setbits(hwdev, MALIDP_SCALE_ENGINE_EN, de_base + MALIDP_DE_DISPLAY_FUNC); > @@ -847,13 +852,18 @@ static long malidp550_se_calc_mclk(struct malidp_hw_device *hwdev, > return ret; > } > > -static int malidp550_enable_memwrite(struct malidp_hw_device *hwdev, > - dma_addr_t *addrs, s32 *pitches, > - int num_planes, u16 w, u16 h, u32 fmt_id, > - const s16 *rgb2yuv_coeffs) > +static int malidp550_enable_memwrite(struct malidp_hw_device *hwdev, u16 w, u16 h, > + struct malidp_mw_connector_state *mw_state) > { > + int num_planes = mw_state->n_planes; > + bool scaling = mw_state->wb_scale_enable; > + dma_addr_t *addrs = mw_state->addrs; > + s32 *pitches = mw_state->pitches; > + u32 fmt_id = mw_state->format; > u32 base = MALIDP550_SE_MEMWRITE_BASE; > u32 de_base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); > + const s16 *rgb2yuv_coeffs = !mw_state->rgb2yuv_initialized ? > + mw_state->rgb2yuv_coeffs : NULL; > > /* enable the scaling engine block */ > malidp_hw_setbits(hwdev, MALIDP_SCALE_ENGINE_EN, de_base + MALIDP_DE_DISPLAY_FUNC); > @@ -876,10 +886,18 @@ static int malidp550_enable_memwrite(struct malidp_hw_device *hwdev, > WARN(1, "Invalid number of planes"); > } > > - malidp_hw_write(hwdev, MALIDP_DE_H_ACTIVE(w) | MALIDP_DE_V_ACTIVE(h), > - MALIDP550_SE_MEMWRITE_OUT_SIZE); > - malidp_hw_setbits(hwdev, MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_EN, > - MALIDP550_SE_CONTROL); > + malidp_hw_clearbits(hwdev, MALIDP_SE_MEMWRITE_EN | MALIDP_SE_MEMWRITE_SCL_EN, > + MALIDP550_SE_CONTROL); > + > + if (scaling) { > + malidp_hw_setbits(hwdev, MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_SCL_EN, > + MALIDP550_SE_CONTROL); > + } else { > + malidp_hw_write(hwdev, MALIDP_DE_H_ACTIVE(w) | MALIDP_DE_V_ACTIVE(h), > + MALIDP550_SE_MEMWRITE_OUT_SIZE); > + malidp_hw_setbits(hwdev, MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_EN, > + MALIDP550_SE_CONTROL); > + } > > if (rgb2yuv_coeffs) { > int i; > @@ -897,7 +915,8 @@ static void malidp550_disable_memwrite(struct malidp_hw_device *hwdev) > { > u32 base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); > > - malidp_hw_clearbits(hwdev, MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_EN, > + malidp_hw_clearbits(hwdev, > + MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_EN | MALIDP_SE_MEMWRITE_SCL_EN, > MALIDP550_SE_CONTROL); > malidp_hw_clearbits(hwdev, MALIDP_SCALE_ENGINE_EN, base + MALIDP_DE_DISPLAY_FUNC); > } > diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h > index 8352a2e..61ddcb5 100644 > --- a/drivers/gpu/drm/arm/malidp_hw.h > +++ b/drivers/gpu/drm/arm/malidp_hw.h > @@ -85,6 +85,7 @@ enum malidp_scaling_coeff_set { > struct malidp_se_config { > u8 scale_enable : 1; > u8 enhancer_enable : 1; > + u8 wb_scale_enable : 1; > u8 hcoeff : 3; > u8 vcoeff : 3; > u8 plane_src_id; > @@ -94,6 +95,19 @@ struct malidp_se_config { > u32 v_init_phase, v_delta_phase; > }; > > +#define to_mw_state(_state) (struct malidp_mw_connector_state *)(_state) > + > +struct malidp_mw_connector_state { > + struct drm_connector_state base; > + dma_addr_t addrs[2]; > + s32 pitches[2]; > + u8 format; > + u8 n_planes; > + bool rgb2yuv_initialized; > + const s16 *rgb2yuv_coeffs; > + bool wb_scale_enable; > +}; > + > /* regmap features */ > #define MALIDP_REGMAP_HAS_CLEARIRQ BIT(0) > #define MALIDP_DEVICE_AFBC_SUPPORT_SPLIT BIT(1) > @@ -206,9 +220,8 @@ struct malidp_hw { > * @param h - height of the output frame > * @param fmt_id - internal format ID of output buffer > */ > - int (*enable_memwrite)(struct malidp_hw_device *hwdev, dma_addr_t *addrs, > - s32 *pitches, int num_planes, u16 w, u16 h, u32 fmt_id, > - const s16 *rgb2yuv_coeffs); > + int (*enable_memwrite)(struct malidp_hw_device *hwdev, u16 w, u16 h, > + struct malidp_mw_connector_state *mw_state); > > /* > * Disable the writing to memory of the next frame's content. > diff --git a/drivers/gpu/drm/arm/malidp_mw.c b/drivers/gpu/drm/arm/malidp_mw.c > index 2865f7a..2120ef1 100644 > --- a/drivers/gpu/drm/arm/malidp_mw.c > +++ b/drivers/gpu/drm/arm/malidp_mw.c > @@ -13,23 +13,13 @@ > #include > #include > #include > +#include