From: Anup Patel <Anup.Patel@wdc.com>
To: Palmer Dabbelt <palmer@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>
Cc: Atish Patra <Atish.Patra@wdc.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Christoph Hellwig <hch@infradead.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Anup Patel <Anup.Patel@wdc.com>
Subject: [PATCH v2 0/3] Allow accessing CSR using CSR number
Date: Sat, 13 Apr 2019 15:38:31 +0000 [thread overview]
Message-ID: <20190413153807.116227-1-anup.patel@wdc.com> (raw)
This patch series adds support to access CSR using both CSR name and
CSR numbers.
Also, we should prefer accessing CSRs using their CSR numbers because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR numbers
as-per RISC-V spec. (e.g. sptbr => CSR_SATP, sbadaddr => CSR_STVAL, etc.)
3. We can access newly added CSRs even if toolchain does not recognize
newly addes CSRs by name. (e.g. BSSTATUS, BSIE, SSIP, etc.)
The patchset can be found in riscv_csr_number_v2 branch of
https//github.com/avpatel/linux.git
Changes since v1:
- Squash PATCH2 into cpatch3
- Added new PATCH2 to add interrupt related SCAUSE defines
in asm/encoding.h
Anup Patel (3):
RISC-V: Add separate asm/encoding.h for spec related defines
RISC-V: Add interrupt related SCAUSE defines in asm/encoding.h
RISC-V: Access CSRs using CSR numbers
arch/riscv/include/asm/csr.h | 67 +++-----------------
arch/riscv/include/asm/encoding.h | 95 ++++++++++++++++++++++++++++
arch/riscv/include/asm/irqflags.h | 10 +--
arch/riscv/include/asm/mmu_context.h | 7 +-
arch/riscv/kernel/entry.S | 22 +++----
arch/riscv/kernel/head.S | 12 ++--
arch/riscv/kernel/irq.c | 9 +--
arch/riscv/kernel/perf_event.c | 4 +-
arch/riscv/kernel/smp.c | 2 +-
arch/riscv/kernel/traps.c | 6 +-
arch/riscv/mm/fault.c | 6 +-
11 files changed, 139 insertions(+), 101 deletions(-)
create mode 100644 arch/riscv/include/asm/encoding.h
--
2.17.1
next reply other threads:[~2019-04-13 15:38 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-13 15:38 Anup Patel [this message]
2019-04-13 15:38 ` [PATCH v2 1/3] RISC-V: Add separate asm/encoding.h for spec related defines Anup Patel
2019-04-15 5:49 ` Christoph Hellwig
2019-04-15 7:29 ` Anup Patel
2019-04-13 15:38 ` [PATCH v2 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/encoding.h Anup Patel
2019-04-13 15:38 ` [PATCH v2 3/3] RISC-V: Access CSRs using CSR numbers Anup Patel
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