From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C9A0C10F14 for ; Mon, 15 Apr 2019 00:48:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 38B3220850 for ; Mon, 15 Apr 2019 00:48:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BB5u/9we" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727279AbfDOAsO (ORCPT ); Sun, 14 Apr 2019 20:48:14 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:38742 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726626AbfDOAre (ORCPT ); Sun, 14 Apr 2019 20:47:34 -0400 Received: by mail-pl1-f194.google.com with SMTP id f36so7703674plb.5; Sun, 14 Apr 2019 17:47:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GRRKksWBg4EhCsv5T20grqrVt88itkyQ3pyd2L45WlA=; b=BB5u/9weWQOpCIDmc+Rw8r0jraD5H0DePbSQL1+PuinWAzQ6ns/swpK4cNQNSt9rAc ly3SjLmi55bH9JqJNpy0t3S9dSbz6gByBjHKtK714ZF7PD/wTpCbvBMEXx4U7XQcWqg5 A16g+jD6kJqtTe5/KXN7rDybZrfH0XT4gYUXMr3hwjjp9c5Bq2GZYIjWBDxDbUsDVEWP IMWbCdMLMqhHnJjRmqu5eb9UGPbyftzWKdiUdBj6Nff2YAMJsF+/CR2OUtdWFnXC7929 p1pC851MYYo0y2OJS5IyDLlDjEbaSTm1d8ZQT+Z+L9/V9JHg06x3qlCpirYIFw0vRLnH l8HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GRRKksWBg4EhCsv5T20grqrVt88itkyQ3pyd2L45WlA=; b=WhzTuJgYl3NzTgdmuVPCzIfaJZ8rSYLaL7b20la4X9t5bBmS2p/qiQiirZMnk0INT8 M5IojC4NAdjEhKadIWXPL89ENN2XV+PbivWJ6kOoxZC8Us6DValiLTJQYnsgkwDOiIHJ CJgR0nKFXfwRji4QcJG/lp0J6AK3ezSUJNt9cyZFG+MIkRKNYBQBV0Y+FExNVBiHiGD0 J4F49fQjuzXG5a5eb0L63SH+A82t63i6OE6Bb07i0TyGHjy+q5ZV+Pm+COllnyojF/Oj YROiLiksBY1wmXZe1VXLkY9WcCj0qS53xvWtmdnwcnWmLG+Cu3Pwj76UV3ZNpW9mdOOm ldQQ== X-Gm-Message-State: APjAAAWj7vMvZ2WI+p51clJstJE5j5xsoCrqPFnpxHz2jo9lyL8LkQbL fhtqBxeyzno420j3RblFrizsx1GV X-Google-Smtp-Source: APXvYqxfJIZVDoFB584oAjLOJnB6U7puhCsYz4KNA0uGaQEYgVIB7Kgdou1tXO3to53X69vB2ydBwA== X-Received: by 2002:a17:902:9a03:: with SMTP id v3mr47617949plp.27.1555289253243; Sun, 14 Apr 2019 17:47:33 -0700 (PDT) Received: from squirtle.lan (c-24-22-235-96.hsd1.wa.comcast.net. [24.22.235.96]) by smtp.gmail.com with ESMTPSA id u17sm66111981pfn.19.2019.04.14.17.47.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 14 Apr 2019 17:47:32 -0700 (PDT) From: Andrey Smirnov To: linux-pci@vger.kernel.org Cc: Andrey Smirnov , Lucas Stach , Lorenzo Pieralisi , Bjorn Helgaas , Chris Healy , linux-kernel@vger.kernel.org Subject: [PATCH v4 05/11] PCI: dwc: imx6: Share PHY debug register definitions Date: Sun, 14 Apr 2019 17:46:26 -0700 Message-Id: <20190415004632.5907-6-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190415004632.5907-1-andrew.smirnov@gmail.com> References: <20190415004632.5907-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Both pcie-designware.c and pci-imx6.c contain custom definitions for PHY debug registers R0/R1 and on top of that there's already a definition for R0 in pcie-designware.h. Move all of the definitions to pcie-designware.h. No functional change intended. Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Chris Healy Cc: Lucas Stach Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org --- drivers/pci/controller/dwc/pci-imx6.c | 6 ++---- drivers/pci/controller/dwc/pcie-designware.c | 12 +++--------- drivers/pci/controller/dwc/pcie-designware.h | 3 +++ 3 files changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index c0867df090f5..eeacdebd9b50 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -103,8 +103,6 @@ struct imx6_pcie { /* PCIe Port Logic registers (memory-mapped) */ #define PL_OFFSET 0x700 -#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) -#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) #define PCIE_PHY_CTRL_DATA_LOC 0 @@ -831,8 +829,8 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) err_reset_phy: dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0), - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1)); + dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), + dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); imx6_pcie_reset_phy(imx6_pcie); return ret; } diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 31f6331ca46f..086e87a40316 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -14,12 +14,6 @@ #include "pcie-designware.h" -/* PCIe Port Logic registers */ -#define PLR_OFFSET 0x700 -#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c) -#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4) -#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29) - int dw_pcie_read(void __iomem *addr, int size, u32 *val) { if (!IS_ALIGNED((uintptr_t)addr, size)) { @@ -334,9 +328,9 @@ int dw_pcie_link_up(struct dw_pcie *pci) if (pci->ops->link_up) return pci->ops->link_up(pci); - val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1); - return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) && - (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))); + val = readl(pci->dbi_base + PCIE_PORT_DEBUG1); + return ((val & PCIE_PORT_DEBUG1_LINK_UP) && + (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING))); } void dw_pcie_setup(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 377f4c0b52da..b33ae13194be 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -41,6 +41,9 @@ #define PCIE_PORT_DEBUG0 0x728 #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f #define PORT_LOGIC_LTSSM_STATE_L0 0x11 +#define PCIE_PORT_DEBUG1 0x72C +#define PCIE_PORT_DEBUG1_LINK_UP BIT(4) +#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29) #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C #define PORT_LOGIC_SPEED_CHANGE BIT(17) -- 2.20.1