From: Sudeep Holla <sudeep.holla@arm.com>
To: Yash Shah <yash.shah@sifive.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
palmer@sifive.com, paul.walmsley@sifive.com,
linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu,
mark.rutland@arm.com, robh+dt@kernel.org,
sachin.ghadi@sifive.com, Sudeep Holla <sudeep.holla@arm.com>
Subject: Re: [PATCH 2/2] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
Date: Thu, 25 Apr 2019 11:17:57 +0100 [thread overview]
Message-ID: <20190425101757.GB8469@e107155-lin> (raw)
In-Reply-To: <1556171696-7741-3-git-send-email-yash.shah@sifive.com>
On Thu, Apr 25, 2019 at 11:24:56AM +0530, Yash Shah wrote:
> The driver currently supports only SiFive FU540-C000 platform.
>
> The initial version of L2 cache controller driver includes:
> - Initial configuration reporting at boot up.
> - Support for ECC related functionality.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
[....]
> +static const struct file_operations l2_fops = {
> + .owner = THIS_MODULE,
> + .open = simple_open,
> + .write = l2_write
> +};
> +
> +static void setup_sifive_debug(void)
> +{
> + sifive_test = debugfs_create_dir("sifive_l2_cache", NULL);
> + if (!sifive_test)
Drop the conditional check above, Greg K H removed lots of them recently.
In his words: When calling debugfs functions, there is no need to ever
check the return value. The function can work or not, but the code
logic should never do something different based on this.
He may not like to see this :)
> + return;
> +
> + if (!debugfs_create_file("sifive_debug_inject_error", 0200,
> + sifive_test, NULL, &l2_fops))
Ditto.
> + debugfs_remove_recursive(sifive_test);
> +}
--
Regards,
Sudeep
next prev parent reply other threads:[~2019-04-25 10:18 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-25 5:54 [PATCH 0/2] L2 cache controller support for SiFive FU540 Yash Shah
2019-04-25 5:54 ` [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller Yash Shah
2019-04-25 10:13 ` Sudeep Holla
2019-04-26 5:50 ` Yash Shah
2019-04-26 9:34 ` Sudeep Holla
2019-04-30 4:20 ` Yash Shah
2019-05-02 0:41 ` Rob Herring
2019-05-02 5:20 ` Yash Shah
2019-05-02 9:10 ` Sudeep Holla
2019-05-02 9:35 ` Yash Shah
2019-04-25 5:54 ` [PATCH 2/2] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs Yash Shah
2019-04-25 10:17 ` Sudeep Holla [this message]
2019-04-26 5:34 ` Yash Shah
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