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[46.139.12.213]) by smtp.gmail.com with ESMTPSA id y125sm34321470wmc.39.2019.04.25.13.08.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 Apr 2019 13:08:32 -0700 (PDT) Date: Thu, 25 Apr 2019 22:08:30 +0200 From: Ingo Molnar To: Fenghua Yu Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , H Peter Anvin , Paolo Bonzini , Dave Hansen , Ashok Raj , Peter Zijlstra , Ravi V Shankar , Xiaoyao Li , Christopherson Sean J , Kalle Valo , Michael Chan , linux-kernel , x86 , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org Subject: Re: [PATCH v8 05/15] x86/msr-index: Define MSR_IA32_CORE_CAPABILITY and split lock detection bit Message-ID: <20190425200830.GD58719@gmail.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> <1556134382-58814-6-git-send-email-fenghua.yu@intel.com> <20190425054511.GA40105@gmail.com> <20190425190148.GA64477@romley-ivt3.sc.intel.com> <20190425194714.GA58719@gmail.com> <20190425195154.GC64477@romley-ivt3.sc.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190425195154.GC64477@romley-ivt3.sc.intel.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Fenghua Yu wrote: > On Thu, Apr 25, 2019 at 09:47:14PM +0200, Ingo Molnar wrote: > > > > * Fenghua Yu wrote: > > > > > On Thu, Apr 25, 2019 at 07:45:11AM +0200, Ingo Molnar wrote: > > > > > > > > * Fenghua Yu wrote: > > > > > > > > > A new MSR_IA32_CORE_CAPABILITY (0xcf) is defined. Each bit in the MSR > > > > > enumerates a model specific feature. Currently bit 5 enumerates split > > > > > lock detection. When bit 5 is 1, split lock detection is supported. > > > > > When the bit is 0, split lock detection is not supported. > > > > > > > > > > Please check the latest Intel 64 and IA-32 Architectures Software > > > > > Developer's Manual for more detailed information on the MSR and the > > > > > split lock detection bit. > > > > > > > > > > Signed-off-by: Fenghua Yu > > > > > --- > > > > > arch/x86/include/asm/msr-index.h | 3 +++ > > > > > 1 file changed, 3 insertions(+) > > > > > > > > > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > > > > > index ca5bc0eacb95..f65ef6f783d2 100644 > > > > > --- a/arch/x86/include/asm/msr-index.h > > > > > +++ b/arch/x86/include/asm/msr-index.h > > > > > @@ -59,6 +59,9 @@ > > > > > #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 > > > > > #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) > > > > > > > > > > +#define MSR_IA32_CORE_CAPABILITY 0x000000cf > > > > > +#define CORE_CAP_SPLIT_LOCK_DETECT BIT(5) /* Detect split lock */ > > > > > > > > Please don't put comments into definitions. > > > > > > I'll remove the comment and change definitions of the MSR and the split lock > > > detection bit as following: > > > > > > +#define MSR_IA32_CORE_CAPABILITY 0x000000cf > > > +#define MSR_IA32_CORE_CAPABILITY_SPLIT_LOCK_DETECT_BIT 5 > > > +#define MSR_IA32_CORE_CAPABILITY_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPABILITY_SPLIT_LOCK_DETECT_BIT) > > > > > > Are these right changes? > > > > I suspect it could be shortened to CORE_CAP as you (partly) did it > > originally. > > IA32_CORE_CAPABILITY is the MSR's exact name in the latest SDM (in Table 2-14): > https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4 > > So can I define the MSR and the bits as follows? > > +#define MSR_IA32_CORE_CAP 0x000000cf > +#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DETECT_BIT 5 > +#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAP_SPLIT_LOCK_DETECT_BIT) Yeah, I suppose that looks OK. Thanks, Ingo